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[Qemu-arm] [PATCH v6 15/21] hw/arm/xilinx_zynqmp: implement SDHCI Spec v
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-arm] [PATCH v6 15/21] hw/arm/xilinx_zynqmp: implement SDHCI Spec v3 |
Date: |
Thu, 11 Jan 2018 17:56:20 -0300 |
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/arm/xlnx-zynqmp.c | 38 +++++++++++++++++++++++++++-----------
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 325642058b..dacf89c566 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -381,22 +381,38 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
- char *bus_name;
-
- object_property_set_bool(OBJECT(&s->sdhci[i]), true,
- "realized", &err);
+ char *bus_name = g_strdup_printf("sd-bus%d", i);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
+ Object *sdhci = OBJECT(&s->sdhci[i]);
+
+ /* Compatible with:
+ * - SD Host Controller Specification Version 3.00
+ * - SDIO Specification Version 3.0
+ * - eMMC Specification Version 4.51
+ *
+ * Host clock rate variable between 0 and 208 MHz
+ * Transfers the data in SDR104, SDR50, DDR50 modes
+ * (SDR104 mode: up to 832Mbits/s using 4 parallel data lines)
+ * Transfers the data in 1 bit and 4 bit SD modes
+ * UHS speed modes, 1.8V
+ * voltage switch, tuning commands
+ */
+ object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
+ object_property_set_bool(sdhci, true, "suspend", &err);
+ object_property_set_bool(sdhci, true, "1v8", &err);
+ object_property_set_bool(sdhci, true, "64bit", &err);
+ object_property_set_uint(sdhci, 0b111, "bus-speed", &err);
+ object_property_set_uint(sdhci, 0b111, "driver-strength", &err);
+ object_property_set_bool(sdhci, true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
- sdhci_addr[i]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
- gic_spi[sdhci_intr[i]]);
+ sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
+ sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
+
/* Alias controller SD bus to the SoC itself */
- bus_name = g_strdup_printf("sd-bus%d", i);
- object_property_add_alias(OBJECT(s), bus_name,
- OBJECT(&s->sdhci[i]), "sd-bus",
+ object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
&error_abort);
g_free(bus_name);
}
--
2.15.1
- [Qemu-arm] [PATCH v6 08/21] sdhci: add v3 capabilities, (continued)
- [Qemu-arm] [PATCH v6 08/21] sdhci: add v3 capabilities, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 09/21] sdhci: rename the hostctl1 register, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 10/21] hw/arm/exynos4210: implement SDHCI Spec v2, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 11/21] hw/arm/xilinx_zynq: implement SDHCI Spec v2, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 12/21] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 13/21] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 14/21] hw/arm/fsl-imx6: implement SDHCI Spec v3, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 15/21] hw/arm/xilinx_zynqmp: implement SDHCI Spec v3,
Philippe Mathieu-Daudé <=
- [Qemu-arm] [PATCH v6 16/21] sdhci: remove the deprecated 'capareg' property, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 17/21] sdhci: add Spec v4.2 register definitions, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 18/21] sdhci: implement the Host Control 2 register for the tunning sequence, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 19/21] sdbus: add trace events, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 20/21] sdhci: implement UHS-I voltage switch, Philippe Mathieu-Daudé, 2018/01/11
- [Qemu-arm] [PATCH v6 21/21] sdhci: implement CMD/DAT[] fields in the Present State register, Philippe Mathieu-Daudé, 2018/01/11