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From: | Richard Henderson |
Subject: | Re: [Qemu-arm] [Qemu-devel] [PATCH v2 07/32] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) |
Date: | Thu, 8 Feb 2018 12:46:25 -0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/08/2018 09:31 AM, Alex Bennée wrote: > This implements the half-precision variants of the across vector > reduction operations. This involves a re-factor of the reduction code > which more closely matches the ARM ARM order (and handles 8 element > reductions). > > Signed-off-by: Alex Bennée <address@hidden> > > -- > v1 > - dropped the advsimd_2a stuff > v2 > - fixed up checkpatch > --- > target/arm/helper-a64.c | 18 ++++++ > target/arm/helper-a64.h | 4 ++ > target/arm/translate-a64.c | 144 > ++++++++++++++++++++++++++++----------------- > 3 files changed, 111 insertions(+), 55 deletions(-) Reviewed-by: Richard Henderson <address@hidden> r~
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