Re: [Qemu-arm] [Qemu-devel] [PATCH v2 12/32] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16

[Richard Henderson]

On 02/08/2018 09:31 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée <address@hidden>
> ---
>  target/arm/helper-a64.c    | 24 ++++++++++++++++++++++++
>  target/arm/helper-a64.h    |  2 ++
>  target/arm/translate-a64.c | 15 +++++++++++++++
>  3 files changed, 41 insertions(+)
> 
> diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
> index 78eeda31d1..bdfcac111f 100644
> --- a/target/arm/helper-a64.c
> +++ b/target/arm/helper-a64.c
> @@ -600,6 +600,30 @@ ADVSIMD_HALFOP(max)
>  ADVSIMD_HALFOP(minnum)
>  ADVSIMD_HALFOP(maxnum)
>  
> +/* Data processing - scalar floating-point and advanced SIMD */
> +float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
> +{
> +    float_status *fpst = fpstp;
> +
> +    a = float16_squash_input_denormal(a, fpst);
> +    b = float16_squash_input_denormal(b, fpst);
> +
> +    if ((float16_is_zero(a) && float16_is_infinity(b)) ||
> +        (float16_is_infinity(a) && float16_is_zero(b))) {
> +        /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
> +        return make_float16((1U << 14) |
> +                            ((float16_val(a) ^ float16_val(b)) & (1U << 
> 15)));

Since you diced all of the structures, are you going to dice all of the (now
pointless) make/val calls?

Otherwise,

Reviewed-by: Richard Henderson <address@hidden>


r~