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From: | Richard Henderson |
Subject: | Re: [Qemu-arm] [Qemu-devel] [PATCH v2 21/32] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 |
Date: | Thu, 8 Feb 2018 14:42:41 -0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/08/2018 09:31 AM, Alex Bennée wrote: > I've re-factored the handle_simd_intfp_conv helper to properly handle > half-precision as well as call plain conversion helpers when we are > not doing fixed point conversion. > > Signed-off-by: Alex Bennée <address@hidden> > --- > target/arm/helper.c | 4 ++ > target/arm/helper.h | 10 ++++ > target/arm/translate-a64.c | 121 > +++++++++++++++++++++++++++++++++++---------- > 3 files changed, 108 insertions(+), 27 deletions(-) Reviewed-by: Richard Henderson <address@hidden> r~
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