Re: [Qemu-arm] [Qemu-devel] [PATCH v2 03/11] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops

[Richard Henderson]

On 02/09/2018 08:58 AM, Peter Maydell wrote:
> For M profile cores, cache maintenance operations are done by
> writing to special registers in the system register space.
> For QEMU, cache operations are always NOPs, since we don't
> implement the cache. Implementing these explicitly avoids
> a spurious LOG_GUEST_ERROR when the guest uses them.
> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  hw/intc/armv7m_nvic.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Reviewed-by: Richard Henderson <address@hidden>


r~