|
From: | Richard Henderson |
Subject: | Re: [Qemu-arm] [Qemu-devel] [PATCH v2 04/11] hw/intc/armv7m_nvic: Implement v8M CPPWR register |
Date: | Fri, 9 Feb 2018 12:37:10 -0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/09/2018 08:58 AM, Peter Maydell wrote: > The Coprocessor Power Control Register (CPPWR) is new in v8M. > It allows software to control whether coprocessors are allowed > to power down and lose their state. QEMU doesn't have any > notion of power control, so we choose the IMPDEF option of > making the whole register RAZ/WI (indicating that no coprocessors > can ever power down and lose state). > > Signed-off-by: Peter Maydell <address@hidden> > --- > hw/intc/armv7m_nvic.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) Reviewed-by: Richard Henderson <address@hidden> r~
[Prev in Thread] | Current Thread | [Next in Thread] |