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[Qemu-arm] [PATCH v2 54/67] target/arm: Implement SVE prefetches
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v2 54/67] target/arm: Implement SVE prefetches |
Date: |
Sat, 17 Feb 2018 10:23:10 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-sve.c | 9 +++++++++
target/arm/sve.decode | 23 +++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index ca49b94924..63c7a0e8d8 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3958,3 +3958,12 @@ static void trans_ST1_zprz(DisasContext *s, arg_ST1_zprz
*a, uint32_t insn)
do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz,
cpu_reg_sp(s, a->rn), fn);
}
+
+/*
+ * Prefetches
+ */
+
+static void trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
+{
+ /* Prefetch is a nop within QEMU. */
+}
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index edd9340c02..f0144aa2d0 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -801,6 +801,29 @@ LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
@rpri_load_msz nreg=0
+# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
+PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
+
+# SVE 32-bit gather prefetch (vector plus immediate)
+PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
+
+# SVE contiguous prefetch (scalar plus immediate)
+PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
+
+# SVE contiguous prefetch (scalar plus scalar)
+PRF 1000010 -- 00 ----- 110 --- ----- 0 ----
+
+### SVE Memory 64-bit Gather Group
+
+# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
+PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
+
+# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
+PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
+
+# SVE 64-bit gather prefetch (vector plus immediate)
+PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
+
### SVE Memory Store Group
# SVE store predicate register
--
2.14.3
- [Qemu-arm] [PATCH v2 49/67] target/arm: Implement SVE FP Multiply-Add Group, (continued)
- [Qemu-arm] [PATCH v2 49/67] target/arm: Implement SVE FP Multiply-Add Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 50/67] target/arm: Implement SVE Floating Point Accumulating Reduction Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 52/67] target/arm: Implement SVE store vector/predicate register, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 51/67] target/arm: Implement SVE load and broadcast element, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 53/67] target/arm: Implement SVE scatter stores, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 54/67] target/arm: Implement SVE prefetches,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 55/67] target/arm: Implement SVE gather loads, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 56/67] target/arm: Implement SVE scatter store vector immediate, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 57/67] target/arm: Implement SVE floating-point compare vectors, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 58/67] target/arm: Implement SVE floating-point arithmetic with immediate, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 59/67] target/arm: Implement SVE Floating Point Multiply Indexed Group, Richard Henderson, 2018/02/17