Re: [Qemu-arm] [PATCH v2 07/67] target/arm: Implement SVE Predicate Logical Operations Group

[Peter Maydell]

On 17 February 2018 at 18:22, Richard Henderson
<address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>

> -void trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
> +static void trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
>  {

Should this be in a previous patch?

>      int nofs = pred_full_reg_offset(s, a->rn);
>      int gofs = pred_full_reg_offset(s, a->pg);
> diff --git a/target/arm/sve.decode b/target/arm/sve.decode
> index 7efaa8fe8e..d92886127a 100644
> --- a/target/arm/sve.decode
> +++ b/target/arm/sve.decode
> @@ -31,6 +31,7 @@
>
>  &rri           rd rn imm
>  &rrr_esz       rd rn rm esz
> +&rprr_s                rd pg rn rm s
>
>  ###########################################################################
>  # Named instruction formats.  These are generally used to
> @@ -39,6 +40,9 @@
>  # Three operand with unused vector element size
>  @rd_rn_rm_e0   ........ ... rm:5 ... ... rn:5 rd:5             &rrr_esz esz=0
>
> +# Three prediate operand, with governing predicate, flag setting

Three what?

> address@hidden ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4    &rprr_s
> +
>  # Basic Load/Store with 9-bit immediate offset
>  @pd_rn_i9      ........ ........ ...... rn:5 . rd:4    \
>                 &rri imm=%imm9_16_10
> @@ -56,6 +60,18 @@ ORR_zzz              00000100 01 1 ..... 001 100 ..... 
> .....         @rd_rn_rm_e0
>  EOR_zzz                00000100 10 1 ..... 001 100 ..... .....         
> @rd_rn_rm_e0
>  BIC_zzz                00000100 11 1 ..... 001 100 ..... .....         
> @rd_rn_rm_e0
>
> +### SVE Predicate Logical Operations Group
> +
> +# SVE predicate logical operations
> +AND_pppp       00100101 0. 00 .... 01 .... 0 .... 0 ....       @pd_pg_pn_pm_s
> +BIC_pppp       00100101 0. 00 .... 01 .... 0 .... 1 ....       @pd_pg_pn_pm_s
> +EOR_pppp       00100101 0. 00 .... 01 .... 1 .... 0 ....       @pd_pg_pn_pm_s
> +SEL_pppp       00100101 0. 00 .... 01 .... 1 .... 1 ....       @pd_pg_pn_pm_s
> +ORR_pppp       00100101 1. 00 .... 01 .... 0 .... 0 ....       @pd_pg_pn_pm_s
> +ORN_pppp       00100101 1. 00 .... 01 .... 0 .... 1 ....       @pd_pg_pn_pm_s
> +NOR_pppp       00100101 1. 00 .... 01 .... 1 .... 0 ....       @pd_pg_pn_pm_s
> +NAND_pppp      00100101 1. 00 .... 01 .... 1 .... 1 ....       @pd_pg_pn_pm_s
> +
>  ### SVE Predicate Misc Group

Otherwise
Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM