[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-pr
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values |
Date: |
Fri, 23 Feb 2018 15:36:08 +0000 |
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 267a9d7e2f..c2bce23fa5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -168,6 +168,7 @@ typedef struct {
* Qn = regs[n].d[1]:regs[n].d[0]
* Dn = regs[n].d[0]
* Sn = regs[n].d[0] bits 31..0
+ * Hn = regs[n].d[0] bits 15..0 for even n, and bits 31..16 for odd n
*
* This corresponds to the architecturally defined mapping between
* the two execution states, and means we do not need to explicitly
--
2.15.1
- [Qemu-arm] [PATCH v3 00/31] Add ARMv8.2 half-precision functions, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 02/31] target/arm/cpu64: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values,
Alex Bennée <=
- [Qemu-arm] [PATCH v3 01/31] include/exec/helper-head.h: support f16 in helper calls, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 05/31] target/arm/helper: pass explicit fpst to set_rmode, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 06/31] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 07/31] arm/translate-a64: handle_3same_64 comment fix, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, Alex Bennée, 2018/02/23