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[Qemu-arm] [PATCH v3 25/31] arm/translate-a64: add FP16 FSQRT to simd_tw
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [PATCH v3 25/31] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 |
Date: |
Fri, 23 Feb 2018 15:36:30 +0000 |
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
v2
remove superfluous helpers
---
target/arm/helper-a64.c | 13 +++++++++++++
target/arm/helper-a64.h | 1 +
target/arm/translate-a64.c | 5 +++++
3 files changed, 19 insertions(+)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 92a0d55a9c..afb25ad20c 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -828,3 +828,16 @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
}
return float16_to_uint16(a, fpst);
}
+
+/*
+ * Square Root and Reciprocal square root
+ */
+
+float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+{
+ float_status *s = fpstp;
+
+ return float16_sqrt(a, s);
+}
+
+
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 339323fc3d..ef4ddfe9d8 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -80,3 +80,4 @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
+DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a7e99e2a2f..ba3926262e 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11388,6 +11388,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x6f: /* FNEG */
need_fpst = false;
break;
+ case 0x7f: /* FSQRT (vector) */
+ break;
default:
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
@@ -11502,6 +11504,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break;
+ case 0x7f: /* FSQRT */
+ gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
+ break;
default:
g_assert_not_reached();
}
--
2.15.1
- Re: [Qemu-arm] [PATCH v3 31/31] arm/translate-a64: add all single op FP16 to handle_fp_1src_half, (continued)
- [Qemu-arm] [PATCH v3 23/31] arm/translate-a64: add FP16 FRECPE, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 19/31] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 22/31] arm/helper.c: re-factor recpe and add recepe_f16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 26/31] arm/helper.c: re-factor rsqrte and add rsqrte_f16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 27/31] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 14/31] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 25/31] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16,
Alex Bennée <=
- [Qemu-arm] [PATCH v3 12/31] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16, Alex Bennée, 2018/02/23
- Re: [Qemu-arm] [PATCH v3 00/31] Add ARMv8.2 half-precision functions, Richard Henderson, 2018/02/23
- Re: [Qemu-arm] [Qemu-devel] [PATCH v3 00/31] Add ARMv8.2 half-precision functions, no-reply, 2018/02/24
- Re: [Qemu-arm] [Qemu-devel] [PATCH v3 00/31] Add ARMv8.2 half-precision functions, no-reply, 2018/02/24