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From: | Richard Henderson |
Subject: | Re: [Qemu-arm] [PATCH v3 19/31] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 |
Date: | Fri, 23 Feb 2018 16:19:00 -0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/23/2018 07:36 AM, Alex Bennée wrote: > I re-use the existing handle_2misc_fcmp_zero handler and tweak it > slightly to deal with the half-precision case. > > Signed-off-by: Alex Bennée <address@hidden> > > --- > v3 > - use size directly wuth read/write_vec_element > - drop unneeded break > - WIP: mess with calculating maxpasses > --- Reviewed-by: Richard Henderson <address@hidden> r~
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