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[Qemu-arm] [PATCH v4 01/31] include/exec/helper-head.h: support f16 in h
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [PATCH v4 01/31] include/exec/helper-head.h: support f16 in helper calls |
Date: |
Tue, 27 Feb 2018 14:38:22 +0000 |
This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
include/exec/helper-head.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index e1fd08f2ba..15b6a68de3 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -26,6 +26,7 @@
#define dh_alias_int i32
#define dh_alias_i64 i64
#define dh_alias_s64 i64
+#define dh_alias_f16 i32
#define dh_alias_f32 i32
#define dh_alias_f64 i64
#define dh_alias_ptr ptr
@@ -38,6 +39,7 @@
#define dh_ctype_int int
#define dh_ctype_i64 uint64_t
#define dh_ctype_s64 int64_t
+#define dh_ctype_f16 float16
#define dh_ctype_f32 float32
#define dh_ctype_f64 float64
#define dh_ctype_ptr void *
@@ -94,6 +96,7 @@
#define dh_is_signed_s32 1
#define dh_is_signed_i64 0
#define dh_is_signed_s64 1
+#define dh_is_signed_f16 0
#define dh_is_signed_f32 0
#define dh_is_signed_f64 0
#define dh_is_signed_tl 0
--
2.15.1
- [Qemu-arm] [PATCH v4 00/31] Add ARMv8.2 half-precision functions, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 02/31] target/arm/cpu64: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 01/31] include/exec/helper-head.h: support f16 in helper calls,
Alex Bennée <=
- [Qemu-arm] [PATCH v4 03/31] target/arm/cpu.h: update comment for half-precision values, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 07/31] arm/translate-a64: handle_3same_64 comment fix, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 04/31] target/arm/cpu.h: add additional float_status flags, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 06/31] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 05/31] target/arm/helper: pass explicit fpst to set_rmode, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 12/31] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 09/31] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16, Alex Bennée, 2018/02/27
- [Qemu-arm] [PATCH v4 16/31] arm/translate-a64: initial decode for simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27