Re: [Qemu-arm] [Qemu-devel] [PATCH v3 15/16] target/arm: Decode t32 simd 3reg and 2reg_scalar extension

[Peter Maydell]

On 28 February 2018 at 19:31, Richard Henderson
<address@hidden> wrote:
> Happily, the bits are in the same places compared to a32.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/translate.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 3ad8b4031c..ba6ab7d287 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -10774,7 +10774,19 @@ static void disas_thumb2_insn(DisasContext *s, 
> uint32_t insn)
>                                 default_exception_el(s));
>              break;
>          }
> -        if (((insn >> 24) & 3) == 3) {
> +        if ((insn & 0xfe000a00) == 0xfc000800
> +            && arm_dc_feature(s, ARM_FEATURE_V8)) {
> +            /* The Thumb2 and ARM encodings are identical.  */
> +            if (disas_neon_insn_3same_ext(s, insn)) {
> +                goto illegal_op;
> +            }
> +        } else if ((insn & 0xff000a00) == 0xfe000800
> +                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
> +            /* The Thumb2 and ARM encodings are identical.  */
> +            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
> +                goto illegal_op;
> +            }
> +        } else if (((insn >> 24) & 3) == 3) {
>              /* Translate into the equivalent ARM encoding.  */
>              insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 
> 28);
>              if (disas_neon_data_insn(s, insn)) {
> --
> 2.14.3

Oh, here they are. If you mention "Thumb decode will be added in
a subsequent commit" in a commit message it helps to avoid confusing
reviewers...

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM