[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide |
Date: |
Fri, 16 Mar 2018 16:31:12 -0400 |
This is a bug fix to ensure 64-bit reads of this register don't read
adjacent data.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9c3b5ef..fb2f983 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -367,7 +367,7 @@ typedef struct CPUARMState {
uint32_t c9_data;
uint64_t c9_pmcr; /* performance monitor control register */
uint64_t c9_pmcnten; /* perf monitor counter enables */
- uint32_t c9_pmovsr; /* perf monitor overflow status */
+ uint64_t c9_pmovsr; /* perf monitor overflow status */
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint64_t c9_pmselr; /* perf monitor counter selection register */
uint64_t c9_pminten; /* perf monitor interrupt enables */
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync, (continued)
- [Qemu-arm] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2018/03/16
- [Qemu-arm] [PATCH v3 07/22] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/03/16
- [Qemu-arm] [PATCH v3 06/22] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2018/03/16
- [Qemu-arm] [PATCH v3 08/22] target/arm: Support multiple EL change hooks, Aaron Lindsay, 2018/03/16
- [Qemu-arm] [PATCH v3 10/22] target/arm: Allow EL change hooks to do IO, Aaron Lindsay, 2018/03/16
- [Qemu-arm] [PATCH v3 09/22] target/arm: Add pre-EL change hooks, Aaron Lindsay, 2018/03/16
- [Qemu-arm] [PATCH v3 11/22] target/arm: Fix bitmask for PMCCFILTR writes, Aaron Lindsay, 2018/03/16
- [Qemu-arm] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide,
Aaron Lindsay <=
[Qemu-arm] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 13/22] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 15/22] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 18/22] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 17/22] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled, Aaron Lindsay, 2018/03/16