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[Qemu-arm] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes |
Date: |
Tue, 17 Apr 2018 16:37:53 -0400 |
It was shifted to the left one bit too few.
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index de3be11..8158d33 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1125,7 +1125,7 @@ static void pmccfiltr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
uint64_t value)
{
pmccntr_op_start(env);
- env->cp15.pmccfiltr_el0 = value & 0x7E000000;
+ env->cp15.pmccfiltr_el0 = value & 0xfc000000;
pmccntr_op_finish(env);
}
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v4 01/21] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, (continued)
- [Qemu-arm] [PATCH v4 01/21] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 02/21] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 05/21] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 04/21] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 06/21] target/arm: Support multiple EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 07/21] target/arm: Add pre-EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 08/21] target/arm: Allow EL change hooks to do IO, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes,
Aaron Lindsay <=
- [Qemu-arm] [PATCH v4 11/21] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 10/21] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 14/21] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 18/21] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 13/21] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 17/21] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 15/21] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 16/21] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 19/21] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/04/17