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[Qemu-arm] [PATCH v3 2/5] target/arm: relax permission checks for HWCAP_
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [PATCH v3 2/5] target/arm: relax permission checks for HWCAP_CPUID registers |
Date: |
Mon, 25 Jun 2018 17:00:06 +0100 |
Although technically not visible to userspace the kernel does make
them visible via trap and emulate. For user mode we can provide the
value directly but we need to relax our permission checks to do this.
Signed-off-by: Alex Bennée <address@hidden>
---
target/arm/helper.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6e6b1762e8..9d81feb124 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5813,7 +5813,19 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
if (r->state != ARM_CP_STATE_AA32) {
int mask = 0;
switch (r->opc1) {
- case 0: case 1: case 2:
+ case 0:
+#ifdef CONFIG_USER_ONLY
+ /* Some AArch64 CPU ID/feature are exported to userspace
+ * by the kernel (see HWCAP_CPUID) */
+ if (r->opc0 == 3 && r->crn == 0 &&
+ (r->crm == 0 ||
+ (r->crm >= 4 && r->crm <= 7))) {
+ mask = PL0_R;
+ break;
+ }
+#endif
+ /* fall-through */
+ case 1: case 2:
/* min_EL EL1 */
mask = PL1_RW;
break;
--
2.17.1
- [Qemu-arm] [PATCH v3 1/5] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space, (continued)
- [Qemu-arm] [PATCH v3 1/5] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space, Alex Bennée, 2018/06/25
- [Qemu-arm] [PATCH v3 4/5] linux-user/elfload: enable HWCAP_CPUID for AArch64, Alex Bennée, 2018/06/25
- [Qemu-arm] [PATCH v3 3/5] target/arm: expose CPUID registers to userspace, Alex Bennée, 2018/06/25
- [Qemu-arm] [PATCH v3 5/5] tests/tcg/aarch64: userspace system register test, Alex Bennée, 2018/06/25
- [Qemu-arm] [PATCH v3 2/5] target/arm: relax permission checks for HWCAP_CPUID registers,
Alex Bennée <=
- Re: [Qemu-arm] [PATCH v3 0/5] support reading some CPUID/CNT registers from user-space, Peter Maydell, 2018/06/28