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[Qemu-arm] [PATCH v2 17/26] target/arm: Implement the access tag cache f
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From: |
Richard Henderson |
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Subject: |
[Qemu-arm] [PATCH v2 17/26] target/arm: Implement the access tag cache flushes |
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Date: |
Sun, 10 Feb 2019 17:08:20 -0800 |
Like the regular data cache flushes, these are nops within qemu.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2d9c070bb3..74bace81e4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5772,6 +5772,54 @@ static const ARMCPRegInfo mte_reginfo[] = {
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
.type = ARM_CP_NO_RAW,
.access = PL0_RW, .readfn = tco_read, .writefn = tco_write },
+ { .name = "IGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "IGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CIGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGVAP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGVADP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CIGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "IGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "IGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CIGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGDVAP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGDVADP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
REGINFO_SENTINEL
};
#endif
--
2.17.2
- [Qemu-arm] [PATCH v2 22/26] target/arm: Create tagged ram when MTE is enabled, (continued)
- [Qemu-arm] [PATCH v2 22/26] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 11/26] target/arm: Implement ADDG, SUBG instructions, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 13/26] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 25/26] target/arm: Enable MTE, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 23/26] target/arm: Add allocation tag storage for user mode, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 26/26] tests/tcg/aarch64: Add mte smoke tests, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 12/26] target/arm: Implement the GMI instruction, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 24/26] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 20/26] tcg: Introduce target-specific page data for user-only, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 14/26] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY, Richard Henderson, 2019/02/10
- [Qemu-arm] [PATCH v2 17/26] target/arm: Implement the access tag cache flushes,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 09/26] target/arm: Suppress tag check for sp+offset, Richard Henderson, 2019/02/10