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Re: [Qemu-arm] [PATCH for-4.0] target/arm: Add sve_access_check to ADDVL
From: |
Amir CHARIF |
Subject: |
Re: [Qemu-arm] [PATCH for-4.0] target/arm: Add sve_access_check to ADDVL, ADDPL, RDVL |
Date: |
Thu, 14 Mar 2019 17:20:52 +0000 |
I don't really know how it usually works here but may I ask why you are turning
my patch into your own and putting me as a reporter ? Are you allowed to do
that ??
I did not just report a bug, I actually provided the fix and submitted a patch,
you can see here that it's timestamped prior to yours
(https://patchew.org/QEMU/ ), I was waiting for your reply to send it to the
mailing list, so is it fair that yours is the one getting reviewed ?
Thanks,
Regards,
Amir
-----Message d'origine-----
De : Richard Henderson <address@hidden>
Envoyé : jeudi 14 mars 2019 17:33
À : Amir CHARIF <address@hidden>
Objet : [PATCH for-4.0] target/arm: Add sve_access_check to ADDVL, ADDPL, RDVL
[Oops, forgot to cc you in the post to qemu-devel.]
This failed to trap when required, which allowed an EL0 guest to execute with
inconsistent data loaded into ZCR_EL1.
Reported-by: Amir Charif <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-sve.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index
3a2eb51566..245cd82621 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -943,24 +943,30 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr
*a)
static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) {
- TCGv_i64 rd = cpu_reg_sp(s, a->rd);
- TCGv_i64 rn = cpu_reg_sp(s, a->rn);
- tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
+ if (sve_access_check(s)) {
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+ tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
+ }
return true;
}
static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) {
- TCGv_i64 rd = cpu_reg_sp(s, a->rd);
- TCGv_i64 rn = cpu_reg_sp(s, a->rn);
- tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
+ if (sve_access_check(s)) {
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+ tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
+ }
return true;
}
static bool trans_RDVL(DisasContext *s, arg_RDVL *a) {
- TCGv_i64 reg = cpu_reg(s, a->rd);
- tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
+ if (sve_access_check(s)) {
+ TCGv_i64 reg = cpu_reg(s, a->rd);
+ tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
+ }
return true;
}
--
2.17.2
- Re: [Qemu-arm] [PATCH for-4.0] target/arm: Add sve_access_check to ADDVL, ADDPL, RDVL,
Amir CHARIF <=