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[Qemu-arm] [RFC PATCH 17/17] Connect the uart reset gpios in the zynq pl
From: |
Damien Hedde |
Subject: |
[Qemu-arm] [RFC PATCH 17/17] Connect the uart reset gpios in the zynq platform |
Date: |
Mon, 25 Mar 2019 12:02:00 +0100 |
Connect the two uart reset inputs to the slcr corresponding outputs.
Signed-off-by: Damien Hedde <address@hidden>
---
hw/arm/xilinx_zynq.c | 14 ++++++++------
include/hw/char/cadence_uart.h | 10 +++++++++-
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index b3b8215759..528d1c42fd 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -166,7 +166,7 @@ static void zynq_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
- DeviceState *dev;
+ DeviceState *dev, *slcr;
SysBusDevice *busdev;
qemu_irq pic[64];
int n;
@@ -211,9 +211,9 @@ static void zynq_init(MachineState *machine)
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
0);
- dev = qdev_create(NULL, "xilinx,zynq_slcr");
- qdev_init_nofail(dev);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
+ slcr = qdev_create(NULL, "xilinx,zynq_slcr");
+ qdev_init_nofail(slcr);
+ sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", 1);
@@ -234,8 +234,10 @@ static void zynq_init(MachineState *machine)
sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
- cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
- cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
+ cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0),
+ slcr, "uart0-rst", 0);
+ cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1),
+ slcr, "uart1-rst", 0);
sysbus_create_varargs("cadence_ttc", 0xF8001000,
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
index 118e3f10de..b7489a711f 100644
--- a/include/hw/char/cadence_uart.h
+++ b/include/hw/char/cadence_uart.h
@@ -51,7 +51,10 @@ typedef struct {
static inline DeviceState *cadence_uart_create(hwaddr addr,
qemu_irq irq,
- Chardev *chr)
+ Chardev *chr,
+ DeviceState *rst_dev,
+ const char *rst_name,
+ int rst_n)
{
DeviceState *dev;
SysBusDevice *s;
@@ -63,6 +66,11 @@ static inline DeviceState *cadence_uart_create(hwaddr addr,
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
+ if (rst_dev) {
+ qdev_connect_gpio_out_named(rst_dev, rst_name, rst_n,
+ qdev_get_gpio_in_named(dev, "rst", 0));
+ }
+
return dev;
}
--
2.21.0
- [Qemu-arm] [RFC PATCH 03/17] make Device and Bus Resettable, (continued)
- [Qemu-arm] [RFC PATCH 03/17] make Device and Bus Resettable, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 09/17] global ResetDomain support for legacy reset handlers, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 06/17] Add function to control reset with gpio inputs, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 10/17] Delete the system ResetDomain at the end of emulation, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 05/17] add vmstate description for device reset state, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 11/17] Put orphan buses in system reset domain, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 12/17] Put default sysbus in system reset domain, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 13/17] hw/misc/zynq_slcr: use standard register definition, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 16/17] Add uart reset support in zynq_slcr, Damien Hedde, 2019/03/25
- [Qemu-arm] [RFC PATCH 17/17] Connect the uart reset gpios in the zynq platform,
Damien Hedde <=
- [Qemu-arm] [RFC PATCH 15/17] Convert zynq's slcr to 3-phases reset, Damien Hedde, 2019/03/25
- Re: [Qemu-arm] [Qemu-devel] [RFC 00/17] multi-phase reset mechanism, no-reply, 2019/03/25