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[Qemu-arm] [PATCH 39/42] target/arm: Convert VJCVT to decodetree
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 39/42] target/arm: Convert VJCVT to decodetree |
Date: |
Thu, 6 Jun 2019 18:46:06 +0100 |
Convert the VJCVT instruction to decodetree.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-vfp.inc.c | 24 ++++++++++++++++++++++++
target/arm/translate.c | 12 +-----------
target/arm/vfp.decode | 4 ++++
3 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index e5b5c3cd6a5..9bc852076a0 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -2418,3 +2418,27 @@ static bool trans_VCVT_int_dp(DisasContext *s,
arg_VCVT_int_dp *a)
tcg_temp_free_ptr(fpst);
return true;
}
+
+static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
+{
+ TCGv_i32 vd;
+ TCGv_i64 vm;
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vm = tcg_temp_new_i64();
+ vd = tcg_temp_new_i32();
+ neon_load_reg64(vm, a->vm);
+ gen_helper_vjcvt(vd, vm, cpu_env);
+ neon_store_reg32(vd, a->vd);
+ tcg_temp_free_i64(vm);
+ tcg_temp_free_i32(vd);
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b98f8f103ae..687ef093f97 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
return 1;
case 15:
switch (rn) {
- case 0 ... 17:
+ case 0 ... 19:
/* Already handled by decodetree */
return 1;
default:
@@ -3085,13 +3085,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
rm_is_dp = false;
break;
- case 0x13: /* vjcvt */
- if (!dp || !dc_isar_feature(aa32_jscvt, s)) {
- return 1;
- }
- rd_is_dp = false;
- break;
-
default:
return 1;
}
@@ -3177,9 +3170,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
switch (op) {
case 15: /* extension space */
switch (rn) {
- case 19: /* vjcvt */
- gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env);
- break;
case 20: /* fshto */
gen_vfp_shto(dp, 16 - rm, 0);
break;
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 6da9a7913da..1a7c9b533de 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -220,3 +220,7 @@ VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
vd=%vd_dp vm=%vm_sp
+
+# VJCVT is always dp to sp
+VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \
+ vd=%vd_sp vm=%vm_dp
--
2.20.1
- Re: [Qemu-arm] [PATCH 33/42] target/arm: Convert VFP comparison insns to decodetree, (continued)
- [Qemu-arm] [PATCH 07/42] target/arm: Convert VMINNM, VMAXNM to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 36/42] target/arm: Convert VFP round insns to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 09/42] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 05/42] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 39/42] target/arm: Convert VJCVT to decodetree,
Peter Maydell <=
- [Qemu-arm] [PATCH 22/42] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 08/42] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 16/42] target/arm: Convert the VFP load/store multiple insns to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 17/42] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 13/42] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/06