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[Qemu-arm] [PATCH v2 17/68] target/arm: Convert ERET
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v2 17/68] target/arm: Convert ERET |
Date: |
Mon, 19 Aug 2019 14:37:04 -0700 |
Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path
to make it clear exactly what's happening -- we hit ALUExceptionReturn
along that path.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 58 ++++++++++++++----------------------------
target/arm/a32.decode | 2 ++
target/arm/t32.decode | 8 ++++++
3 files changed, 29 insertions(+), 39 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f0fa5253b6..cb7b35489f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8474,6 +8474,23 @@ static bool trans_CLZ(DisasContext *s, arg_CLZ *a)
return true;
}
+static bool trans_ERET(DisasContext *s, arg_ERET *a)
+{
+ TCGv_i32 tmp;
+
+ if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V7VE)) {
+ return false;
+ }
+ if (s->current_el == 2) {
+ /* ERET from Hyp uses ELR_Hyp, not LR */
+ tmp = load_cpu_field(elr_el[2]);
+ } else {
+ tmp = load_reg(s, 14);
+ }
+ gen_exception_return(s, tmp);
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -8768,29 +8785,10 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
case 0x4: /* crc32 */
/* All done in decodetree. Illegal ops reach here. */
goto illegal_op;
- case 0x5:
- /* Saturating addition and subtraction. */
+ case 0x5: /* Saturating addition and subtraction. */
+ case 0x6: /* ERET */
/* All done in decodetree. Reach here for illegal ops. */
goto illegal_op;
- case 0x6: /* ERET */
- if (op1 != 3) {
- goto illegal_op;
- }
- if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) {
- goto illegal_op;
- }
- if ((insn & 0x000fff0f) != 0x0000000e) {
- /* UNPREDICTABLE; we choose to UNDEF */
- goto illegal_op;
- }
-
- if (s->current_el == 2) {
- tmp = load_cpu_field(elr_el[2]);
- } else {
- tmp = load_reg(s, 14);
- }
- gen_exception_return(s, tmp);
- break;
case 7:
{
int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
@@ -10586,24 +10584,6 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
case 4: /* bxj, in decodetree */
goto illegal_op;
case 5: /* Exception return. */
- if (IS_USER(s)) {
- goto illegal_op;
- }
- if (rn != 14 || rd != 15) {
- goto illegal_op;
- }
- if (s->current_el == 2) {
- /* ERET from Hyp uses ELR_Hyp, not LR */
- if (insn & 0xff) {
- goto illegal_op;
- }
- tmp = load_cpu_field(elr_el[2]);
- } else {
- tmp = load_reg(s, rn);
- tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
- }
- gen_exception_return(s, tmp);
- break;
case 6: /* MRS, in decodetree */
case 7: /* MSR, in decodetree */
goto illegal_op;
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 182f2b6725..52a66dd1d5 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -211,3 +211,5 @@ BXJ .... 0001 0010 1111 1111 1111 0010 ....
@rm
BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm
CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm
+
+ERET ---- 0001 0110 0000 0000 0000 0110 1110
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 67724efe4b..6236d28b99 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -218,4 +218,12 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ....
@rdm
MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8
}
BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r
+ {
+ # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
+ # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET.
+ # The distinction between the two only matters for Hyp mode.
+ ERET 1111 0011 1101 1110 1000 1111 0000 0000
+ SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \
+ &s_rri_rot rot=0 s=1 rd=15 rn=14
+ }
}
--
2.17.1
- Re: [Qemu-arm] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints, (continued)
- [Qemu-arm] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 16/68] target/arm: Convert CLZ, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 17/68] target/arm: Convert ERET,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW, Richard Henderson, 2019/08/19