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Re: [Qemu-arm] [PATCH v2 17/68] target/arm: Convert ERET
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-arm] [PATCH v2 17/68] target/arm: Convert ERET |
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Date: |
Fri, 23 Aug 2019 13:25:21 +0100 |
On Mon, 19 Aug 2019 at 22:38, Richard Henderson
<address@hidden> wrote:
>
> Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path
> to make it clear exactly what's happening -- we hit ALUExceptionReturn
> along that path.
>
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [Qemu-arm] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register), (continued)
- [Qemu-arm] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 16/68] target/arm: Convert CLZ, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 17/68] target/arm: Convert ERET, Richard Henderson, 2019/08/19
- Re: [Qemu-arm] [PATCH v2 17/68] target/arm: Convert ERET,
Peter Maydell <=
- [Qemu-arm] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW, Richard Henderson, 2019/08/19