[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v3 33/69] target/arm: Convert SVC
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v3 33/69] target/arm: Convert SVC |
Date: |
Wed, 28 Aug 2019 12:04:20 -0700 |
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 19 +++++++++++++------
target/arm/a32.decode | 4 ++++
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index fb0e875917..eb4384618c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10048,6 +10048,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return true;
}
+/*
+ * Supervisor call
+ */
+
+static bool trans_SVC(DisasContext *s, arg_SVC *a)
+{
+ gen_set_pc_im(s, s->base.pc_next);
+ s->svc_imm = a->imm;
+ s->base.is_jmp = DISAS_SWI;
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -10315,6 +10327,7 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
case 0x09:
case 0xa:
case 0xb:
+ case 0xf:
/* All done in decodetree. Reach here for illegal ops. */
goto illegal_op;
case 0xc:
@@ -10330,12 +10343,6 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
goto illegal_op;
}
break;
- case 0xf:
- /* swi */
- gen_set_pc_im(s, s->base.pc_next);
- s->svc_imm = extract32(insn, 0, 24);
- s->base.is_jmp = DISAS_SWI;
- break;
default:
illegal_op:
unallocated_encoding(s);
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 62c6f8562e..0bd952c069 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -528,3 +528,7 @@ LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16
&ldst_block
B .... 1010 ........................ @branch
BL .... 1011 ........................ @branch
+
+# Supervisor call
+
+SVC ---- 1111 imm:24 &i
--
2.17.1
- [Qemu-arm] [PATCH v3 29/69] target/arm: Diagnose writeback register in list for LDM for v7, (continued)
- [Qemu-arm] [PATCH v3 29/69] target/arm: Diagnose writeback register in list for LDM for v7, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 27/69] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 25/69] target/arm: Convert packing, unpacking, saturation, and reversal, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 31/69] target/arm: Diagnose base == pc for LDM/STM, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 32/69] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 30/69] target/arm: Diagnose too few registers in list for LDM/STM, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 20/69] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 26/69] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 28/69] target/arm: Convert LDM, STM, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 34/69] target/arm: Convert RFE and SRS, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 33/69] target/arm: Convert SVC,
Richard Henderson <=
- [Qemu-arm] [PATCH v3 40/69] target/arm: Convert Table Branch, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 37/69] target/arm: Convert SETEND, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm), Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move (two high registers), Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 56/69] target/arm: Convert T16, extract, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 58/69] target/arm: Convert T16, Reverse bytes, Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 49/69] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 36/69] target/arm: Convert CPS (privileged), Richard Henderson, 2019/08/28
- [Qemu-arm] [PATCH v3 41/69] target/arm: Convert SG, Richard Henderson, 2019/08/28