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Re: [PATCH v24 00/10] Add ARMv8 RAS virtualization support in QEMU
From: |
Peter Maydell |
Subject: |
Re: [PATCH v24 00/10] Add ARMv8 RAS virtualization support in QEMU |
Date: |
Fri, 21 Feb 2020 14:09:55 +0000 |
On Mon, 17 Feb 2020 at 13:10, Dongjiu Geng <address@hidden> wrote:
>
> In the ARMv8 platform, the CPU error types includes synchronous external
> abort(SEA) and SError Interrupt (SEI). If exception happens in guest, host
> does not know the detailed information of guest, so it is expected that guest
> can do the recovery.
> For example, if an exception happens in a guest user-space application, host
> does
> not know which application encounters errors, only guest knows it.
>
> For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify userspace.
> After user space gets the notification, it will record the CPER into guest
> GHES
> buffer and inject an exception or IRQ to guest.
>
> In the current implementation, if the type of SIGBUS is BUS_MCEERR_AR, we will
> treat it as a synchronous exception, and notify guest with ARMv8 SEA
> notification type after recording CPER into guest.
Hi; I have reviewed the remaining arm bit of this series (patch 9),
and made some comments on patch 1. Still to be reviewed are
patches 4, 5, 6, 8: I'm going to assume that Michael or Igor
will look at those.
thanks
-- PMM
- Re: [PATCH v24 04/10] ACPI: Build related register address fields via hardware error fw_cfg blob, (continued)
- [PATCH v24 03/10] docs: APEI GHES generation and CPER record description, Dongjiu Geng, 2020/02/17
- [PATCH v24 08/10] ACPI: Record Generic Error Status Block(GESB) table, Dongjiu Geng, 2020/02/17
- [PATCH v24 06/10] ACPI: Record the Generic Error Status Block address, Dongjiu Geng, 2020/02/17
- [PATCH v24 10/10] MAINTAINERS: Add ACPI/HEST/GHES entries, Dongjiu Geng, 2020/02/17
- [PATCH v24 09/10] target-arm: kvm64: handle SIGBUS signal from kernel or KVM, Dongjiu Geng, 2020/02/17
- Re: [PATCH v24 00/10] Add ARMv8 RAS virtualization support in QEMU,
Peter Maydell <=