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[PATCH 3/4] target/arm: Implement SVE2 SUBHNB, SUBHNT
From: |
Stephen Long |
Subject: |
[PATCH 3/4] target/arm: Implement SVE2 SUBHNB, SUBHNT |
Date: |
Fri, 17 Apr 2020 12:22:30 -0400 |
Signed-off-by: Stephen Long <address@hidden>
---
target/arm/helper-sve.h | 8 ++++++++
target/arm/sve.decode | 2 ++
target/arm/sve_helper.c | 10 ++++++++++
target/arm/translate-sve.c | 3 +++
4 files changed, 23 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 5d5542a82a..00e3706da0 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2532,6 +2532,14 @@ DEF_HELPER_FLAGS_4(sve2_raddhnt_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_raddhnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_raddhnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_subhnt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_subhnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve2_match_ppzz_b, TCG_CALL_NO_RWG,
i32, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_match_ppzz_h, TCG_CALL_NO_RWG,
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 9d82677808..75996897a1 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1327,6 +1327,8 @@ ADDHNB 01000101 .. 1 ..... 011 000 ..... .....
@rd_rn_rm
ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
+SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
+SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
### SVE2 Character Match
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index f92b8dd312..f6e7694b9f 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2049,6 +2049,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t
desc) \
#define DO_ADDHN(N, M, SH) ((N + M) >> SH)
#define DO_RADDHN(N, M, SH) ((N + M + (1 << (SH - 1))) >> SH)
+#define DO_SUBHN(N, M, SH) ((N - M) >> SH)
DO_BINOPNB(sve2_addhnb_h, uint16_t, uint8_t, 8, DO_ADDHN)
DO_BINOPNB(sve2_addhnb_s, uint32_t, uint16_t, 16, DO_ADDHN)
@@ -2066,6 +2067,15 @@ DO_BINOPNT(sve2_raddhnt_h, uint16_t, uint8_t, 8, H1_2,
H1, DO_RADDHN)
DO_BINOPNT(sve2_raddhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_RADDHN)
DO_BINOPNT(sve2_raddhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_RADDHN)
+DO_BINOPNB(sve2_subhnb_h, uint16_t, uint8_t, 8, DO_SUBHN)
+DO_BINOPNB(sve2_subhnb_s, uint32_t, uint16_t, 16, DO_SUBHN)
+DO_BINOPNB(sve2_subhnb_d, uint64_t, uint32_t, 32, DO_SUBHN)
+
+DO_BINOPNT(sve2_subhnt_h, uint16_t, uint8_t, 8, H1_2, H1, DO_SUBHN)
+DO_BINOPNT(sve2_subhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_SUBHN)
+DO_BINOPNT(sve2_subhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_SUBHN)
+
+#undef DO_SUBHN
#undef DO_RADDHN
#undef DO_ADDHN
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index a36eb9cf98..4081fcb873 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7519,6 +7519,9 @@ DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt)
DO_SVE2_ZZZ_NARROW(RADDHNB, raddhnb)
DO_SVE2_ZZZ_NARROW(RADDHNT, raddhnt)
+DO_SVE2_ZZZ_NARROW(SUBHNB, subhnb)
+DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt)
+
static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
gen_helper_gvec_flags_4 *fn)
{
--
2.17.1
- [PATCH 0/4] target/arm: Implement last SVE2 narrowing section, Stephen Long, 2020/04/17
- [PATCH 1/4] target/arm: Implement SVE2 ADDHNB, ADDHNT, Stephen Long, 2020/04/17
- [PATCH 2/4] target/arm: Implement SVE2 RADDHNB, RADDHNT, Stephen Long, 2020/04/17
- [PATCH 3/4] target/arm: Implement SVE2 SUBHNB, SUBHNT,
Stephen Long <=
- [PATCH 4/4] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Stephen Long, 2020/04/17
- Re: [PATCH 0/4] target/arm: Implement last SVE2 narrowing section, Richard Henderson, 2020/04/19