Re: [PATCH] target/arm: Use correct variable for setting 'max' cpu's MIDR_EL1

[Laurent Desnogues]

On Thu, Apr 23, 2020 at 2:44 PM Philippe Mathieu-Daudé <address@hidden> wrote:
>
> MIDR_EL1 is a 32-bit register.

In fact MIDR_EL1 a 64-bit system register with the top 32-bit being RES0.

So the right fix might be to change midr field size, just to be future proof :-)

But if we stick to a 32-bit midr then:

Reviewed-by: Laurent Desnogues <address@hidden>

Thanks,

Laurent

> This fixes when compiling with -Werror=conversion:
>
>   target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
>   target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long 
> unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value 
> [-Werror=conversion]
>     628 |         cpu->midr = t;
>         |                     ^
>
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
> ---
>  target/arm/cpu64.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 95d0c8c101..4eb0a9030e 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -620,12 +620,12 @@ static void aarch64_max_initfn(Object *obj)
>           * code needs to distinguish this QEMU CPU from other software
>           * implementations, though this shouldn't be needed.
>           */
> -        t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
> -        t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
> -        t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
> -        t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
> -        t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
> -        cpu->midr = t;
> +        u = FIELD_DP32(0, MIDR_EL1, IMPLEMENTER, 0);
> +        u = FIELD_DP32(u, MIDR_EL1, ARCHITECTURE, 0xf);
> +        u = FIELD_DP32(u, MIDR_EL1, PARTNUM, 'Q');
> +        u = FIELD_DP32(u, MIDR_EL1, VARIANT, 0);
> +        u = FIELD_DP32(u, MIDR_EL1, REVISION, 0);
> +        cpu->midr = u;
>
>          t = cpu->isar.id_aa64isar0;
>          t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
> --
> 2.21.1
>
>