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Re: [PATCH v3 13/18] target/arm: Update contiguous first-fault and no-fa
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 13/18] target/arm: Update contiguous first-fault and no-fault loads |
Date: |
Mon, 27 Apr 2020 17:32:42 +0100 |
On Mon, 27 Apr 2020 at 17:16, Richard Henderson
<address@hidden> wrote:
>
> On 4/27/20 4:03 AM, Peter Maydell wrote:
> > On Wed, 22 Apr 2020 at 05:33, Richard Henderson
> > <address@hidden> wrote:
> >>
> >> With sve_cont_ldst_pages, the differences between first-fault and no-fault
> >> are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
> >> to make progress through pages with TLB_WATCHPOINT set when the watchpoint
> >> does not actually fire.
> >>
> >> Signed-off-by: Richard Henderson <address@hidden>
> >
> >
> >> /*
> >> - * Perform one normal read, which will fault or not.
> >> - * But it is likely to bring the page into the tlb.
> >> + * From this point on, all memory operations are MemSingleNF.
> >> + *
> >> + * Per the MemSingleNF pseudocode, a no-fault load from Device memory
> >> + * must not actually hit the bus -- it returns (UNKNOWN, FAULT)
> >> instead.
> >> + * If you map non-RAM with Normal memory attributes and do a NF
> >> + * load then it should access the bus -- but doing so is illegal.
> >> + *
> >> + * While we do not have access to the memory attributes from the PTE
> >> + * to tell Device memory from Normal memory, we can validly assume
> >> that
> >> + * non-RAM has been mapped as Device memory. Thus we indicate fault
> >> + * on all MMIO.
> >
> > I still don't understand why this is right. All non-RAM is MMIO
> > but not all MMIO is non-RAM; so you might have something that's
> > MMIO (at least for the moment) and has been mapped Normal. That
> > shouldn't fault.
>
> Everything that must go through the slow path has TLB_MMIO set.
Yes. But not everything that goes through the slow path is Device memory.
We can (should) fault on all accesses to Device memory, but we can't
fault on all accesses that are slow-pathed, because some of them could
be entirely valid Normal memory.
> What you're thinking of, romd, has TLB_MMIO set on the write comparator but
> not
> the read comparator.
True when the romd device is in 'romd mode', ie mr->romd_mode is
true. Otherwise memory_region_is_romd() returns false and
tlb_set_page_with_attrs() treats it like normal MMIO, because
both read and write must take the slow path. (For flash this
happens when it is put into programming mode and reads from
the memory region are no longer simple reads from the backing
host RAM.)
thanks
-- PMM
- [PATCH v3 09/18] target/arm: Adjust interface of sve_ld1_host_fn, (continued)
- [PATCH v3 09/18] target/arm: Adjust interface of sve_ld1_host_fn, Richard Henderson, 2020/04/22
- [PATCH v3 08/18] target/arm: Add sve infrastructure for page lookup, Richard Henderson, 2020/04/22
- [PATCH v3 10/18] target/arm: Use SVEContLdSt in sve_ld1_r, Richard Henderson, 2020/04/22
- [PATCH v3 12/18] target/arm: Use SVEContLdSt for multi-register contiguous loads, Richard Henderson, 2020/04/22
- [PATCH v3 07/18] target/arm: Drop manual handling of set/clear_helper_retaddr, Richard Henderson, 2020/04/22
- [PATCH v3 14/18] target/arm: Use SVEContLdSt for contiguous stores, Richard Henderson, 2020/04/22
- [PATCH v3 13/18] target/arm: Update contiguous first-fault and no-fault loads, Richard Henderson, 2020/04/22
[PATCH v3 15/18] target/arm: Reuse sve_probe_page for gather first-fault loads, Richard Henderson, 2020/04/22
[PATCH v3 16/18] target/arm: Reuse sve_probe_page for scatter stores, Richard Henderson, 2020/04/22
[PATCH v3 18/18] target/arm: Remove sve_memopidx, Richard Henderson, 2020/04/22
[PATCH v3 11/18] target/arm: Handle watchpoints in sve_ld1_r, Richard Henderson, 2020/04/22
[PATCH v3 17/18] target/arm: Reuse sve_probe_page for gather loads, Richard Henderson, 2020/04/22
Re: [PATCH v3 00/18] target/arm: sve load/store improvements, no-reply, 2020/04/22