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[PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt
From: |
Sai Pavan Boddu |
Subject: |
[PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register |
Date: |
Mon, 4 May 2020 19:36:06 +0530 |
Mask all interrupt on reset.
Signed-off-by: Sai Pavan Boddu <address@hidden>
---
hw/net/cadence_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 9eb72a2..ac3a553 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1348,6 +1348,7 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_DESCONF2] = 0x2ab12800;
s->regs[GEM_DESCONF5] = 0x002f2045;
s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
+ s->regs[GEM_INT_Q1_MASK] = 0x00000CE6;
if (s->num_priority_queues > 1) {
queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
--
2.7.4
- [PATCH v2 04/10] net: cadence_gem: Define access permission for interrupt registers, (continued)
- [PATCH v2 04/10] net: cadence_gem: Define access permission for interrupt registers, Sai Pavan Boddu, 2020/05/04
- [PATCH v2 05/10] net: cadence_gem: Set ISR according to queue in use, Sai Pavan Boddu, 2020/05/04
- [PATCH v2 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg, Sai Pavan Boddu, 2020/05/04
- [PATCH v2 06/10] net: cadence_gem: Add support for jumbo frames, Sai Pavan Boddu, 2020/05/04
- [PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register,
Sai Pavan Boddu <=
- [PATCH v2 09/10] net: cadence_gem: TX_LAST bit should be set by guest, Sai Pavan Boddu, 2020/05/04
- [PATCH v2 10/10] net: cadence_gem: Fix RX address filtering, Sai Pavan Boddu, 2020/05/04
- Re: [PATCH v2 00/10] Cadence GEM Fixes, Ramon Fried, 2020/05/04
- Re: [PATCH v2 00/10] Cadence GEM Fixes, no-reply, 2020/05/05