[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: v8.1M cpu emulation and target-arm feature-identification strategy
From: |
Peter Maydell |
Subject: |
Re: v8.1M cpu emulation and target-arm feature-identification strategy |
Date: |
Wed, 5 Aug 2020 20:02:50 +0100 |
On Wed, 5 Aug 2020 at 18:00, Richard Henderson
<richard.henderson@linaro.org> wrote:
> I've always assumed we'd never get rid of all of them.
>
> Older ones like XSCALE are obvious, but I don't think there's a clear
> indicator
> for V{5,6,7,8} either.
MIDR.Architecture lets you distinguish v4/v4T/v5/v5T/v5TE/v5TEJ/v6,
and there are also some separate per-feature ID register fields for
things which we currently hang off those ARM_FEATURE_Vx flags.
In theory all the v7-and-later stuff should have its own ID register
field...
Regardless, it's hard to see a clear benefit from a hypothetical
concerted effort to convert all the ARM_FEATURE_* uses to ID
register checks, though we might choose to convert a few here
and there if we need to overhaul the code anyway.
thanks
-- PMM