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Re: [PATCH 20/22] target/arm: Implement new VFP fp16 insn VMOVX
From: |
Richard Henderson |
Subject: |
Re: [PATCH 20/22] target/arm: Implement new VFP fp16 insn VMOVX |
Date: |
Tue, 25 Aug 2020 12:25:27 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/24/20 7:29 AM, Peter Maydell wrote:
> The fp16 extension includes a new instruction VMOVX, which copies the
> upper 16 bits of a 32-bit source VFP register into the lower 16
> bits of the destination and zeroes the high half of the destination.
> Implement it.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/vfp-uncond.decode | 3 +++
> target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++
> 2 files changed, 28 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- Re: [PATCH 13/22] target/arm: Make VFP_CONV_FIX macros take separate float type and float size, (continued)
- [PATCH 16/22] target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode, Peter Maydell, 2020/08/24
- [PATCH 17/22] target/arm: Implement VFP fp16 VSEL, Peter Maydell, 2020/08/24
- [PATCH 18/22] target/arm: Implement VFP fp16 VRINT*, Peter Maydell, 2020/08/24
- [PATCH 19/22] target/arm: Implement new VFP fp16 insn VINS, Peter Maydell, 2020/08/24
- [PATCH 20/22] target/arm: Implement new VFP fp16 insn VMOVX, Peter Maydell, 2020/08/24
- Re: [PATCH 20/22] target/arm: Implement new VFP fp16 insn VMOVX,
Richard Henderson <=
- [PATCH 22/22] target/arm: Enable FP16 in '-cpu max', Peter Maydell, 2020/08/24
- [PATCH 21/22] target/arm: Implement VFP fp16 VMOV between gp and halfprec registers, Peter Maydell, 2020/08/24