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Re: [PATCH v1 2/2] target/microblaze: Improve transaction failure handli
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From: |
Edgar E. Iglesias |
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Subject: |
Re: [PATCH v1 2/2] target/microblaze: Improve transaction failure handling |
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Date: |
Mon, 31 Aug 2020 14:41:28 +0200 |
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User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Fri, Aug 28, 2020 at 01:34:08PM -0700, Richard Henderson wrote:
> On 8/28/20 4:39 AM, Edgar E. Iglesias wrote:
> > + if ((access_type == MMU_INST_FETCH && cpu->cfg.iopb_bus_exception) ||
> > + (access_type != MMU_INST_FETCH && cpu->cfg.dopb_bus_exception)) {
> > + cpu_restore_state(cs, retaddr, true);
> > + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ?
> > + ESR_EC_INSN_BUS : ESR_EC_DATA_BUS;
> > + env->sregs[SR_EAR] = addr;
> > + helper_raise_exception(env, EXCP_HW_EXCP);
>
> I think it's better to use cpu_loop_exit_restore, adding the one line for
> cs->exception_index from helper_raise_exception.
>
OK, let's use the patch you posted:
https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg07630.html
Thanks,
Edgar