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[RFC v3 10/10] target/arm: Add CPU features to query-cpu-model-expansion
From: |
Peng Liang |
Subject: |
[RFC v3 10/10] target/arm: Add CPU features to query-cpu-model-expansion |
Date: |
Mon, 2 Nov 2020 13:40:55 +0800 |
Add CPU features to the result of query-cpu-model-expansion so that
other applications (such as libvirt) can know the supported CPU
features.
Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
target/arm/monitor.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index 169d8a64b651..7950206352f1 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -104,6 +104,10 @@ static const char *cpu_model_advertised_features[] = {
"sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
"sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
"kvm-no-adjvtime", "kvm-steal-time",
+ "aes", "sha1", "sha2", "crc32", "atomics", "asimdrdm", "sha3", "sm3",
"sm4",
+ "asimddp", "asimdfhm", "flagm", "rng", "dcpop", "jscvt", "fcma", "lrcpc",
+ "frint", "sb", "i8mm", "bf16", "dgh", "fp", "asimd", "dit", "bt", "sbss",
+ "uscat", "fphp", "asimdhp", "pmull", "sha512", "flagm2", "dcpodp",
"ilrcpc",
NULL
};
--
2.26.2
- [RFC v3 00/10] Support disable/enable CPU features for AArch64, Peng Liang, 2020/11/02
- [RFC v3 03/10] target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest, Peng Liang, 2020/11/02
- [RFC v3 02/10] target/arm: Update ID fields, Peng Liang, 2020/11/02
- [RFC v3 01/10] linux-header: Introduce KVM_CAP_ARM_CPU_FEATURE, Peng Liang, 2020/11/02
- [RFC v3 04/10] target/arm: convert isar regs to array, Peng Liang, 2020/11/02
- [RFC v3 05/10] target/arm: Introduce kvm_arm_cpu_feature_supported, Peng Liang, 2020/11/02
- [RFC v3 10/10] target/arm: Add CPU features to query-cpu-model-expansion,
Peng Liang <=
- [RFC v3 08/10] target/arm: Introduce user_mask to indicate whether the feature is set explicitly, Peng Liang, 2020/11/02
- [RFC v3 09/10] target/arm: introduce CPU feature dependency mechanism, Peng Liang, 2020/11/02
- [RFC v3 06/10] target/arm: register CPU features for property, Peng Liang, 2020/11/02
- [RFC v3 07/10] target/arm: Allow ID registers to synchronize to KVM, Peng Liang, 2020/11/02