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[PATCH 16/17] target/arm: enable Secure EL2 in max CPU
From: |
remi . denis . courmont |
Subject: |
[PATCH 16/17] target/arm: enable Secure EL2 in max CPU |
Date: |
Mon, 9 Nov 2020 16:10:19 +0200 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 649213082f..8c3749268e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -641,6 +641,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
cpu->isar.id_aa64pfr0 = t;
t = cpu->isar.id_aa64pfr1;
--
2.29.2
- Re: [PATCH 09/17] target/arm: add MMU stage 1 for Secure EL2, (continued)
- [PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, remi . denis . courmont, 2020/11/09
- [PATCH 15/17] target/arm: add ARMv8.4-SEL2 extension, remi . denis . courmont, 2020/11/09
- [PATCH 17/17] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2020/11/09
- [PATCH 10/17] target/arm: add ARMv8.4-SEL2 system registers, remi . denis . courmont, 2020/11/09
- [PATCH 12/17] target/arm: secure stage 2 translation regime, remi . denis . courmont, 2020/11/09
- [PATCH 13/17] target/arm: handle VMID change in secure state, remi . denis . courmont, 2020/11/09
- [PATCH 16/17] target/arm: enable Secure EL2 in max CPU,
remi . denis . courmont <=
- Re: [PATCHv2 00/17] ARM Secure EL2 extension, no-reply, 2020/11/09