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[PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restri
From: |
Peter Maydell |
Subject: |
[PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restrictions |
Date: |
Thu, 19 Nov 2020 21:55:55 +0000 |
For M-profile before v8.1M, the only valid register for VMSR/VMRS is
the FPSCR. We have a comment that states this, but the actual logic
to forbid accesses for any other register value is missing, so we
would end up with A-profile style behaviour. Add the missing check.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.c.inc | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 2a67ed0f6e2..e100182a32c 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -622,7 +622,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS
*a)
* Accesses to R15 are UNPREDICTABLE; we choose to undef.
* (FPSCR -> r15 is a special case which writes to the PSR flags.)
*/
- if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
+ if (a->reg != ARM_VFP_FPSCR) {
+ return false;
+ }
+ if (a->rt == 15 && !a->l) {
return false;
}
}
--
2.20.1
- [PATCH v2 00/28] target/arm: Implement v8.1M and Cortex-M55, Peter Maydell, 2020/11/19
- [PATCH v2 02/28] target/arm: Implement v8.1M PXN extension, Peter Maydell, 2020/11/19
- [PATCH v2 03/28] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, Peter Maydell, 2020/11/19
- [PATCH v2 04/28] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/11/19
- [PATCH v2 01/28] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault, Peter Maydell, 2020/11/19
- [PATCH v2 05/28] target/arm: Implement CLRM instruction, Peter Maydell, 2020/11/19
- [PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restrictions,
Peter Maydell <=
- [PATCH v2 07/28] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/11/19
- [PATCH v2 09/28] target/arm: Implement VLDR/VSTR system register, Peter Maydell, 2020/11/19
- [PATCH v2 08/28] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/11/19
- [PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant, Peter Maydell, 2020/11/19
- [PATCH v2 12/28] target/arm: Factor out preserve-fp-state from full_vfp_access_check(), Peter Maydell, 2020/11/19
- [PATCH v2 10/28] target/arm: Implement M-profile FPSCR_nzcvqc, Peter Maydell, 2020/11/19
- [PATCH v2 17/28] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures, Peter Maydell, 2020/11/19
- [PATCH v2 16/28] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry, Peter Maydell, 2020/11/19
- [PATCH v2 13/28] target/arm: Implement FPCXT_S fp system register, Peter Maydell, 2020/11/19