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[PATCH v2 07/24] target/arm: Enforce word alignment for LDRD/STRD
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 07/24] target/arm: Enforce word alignment for LDRD/STRD |
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Date: |
Tue, 8 Dec 2020 12:01:01 -0600 |
Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f6007c23a6..9ca06cb373 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6468,13 +6468,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr
*a)
addr = op_addr_rr_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt + 1, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6497,13 +6497,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr
*a)
addr = op_addr_rr_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, a->rt + 1);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
op_addr_rr_post(s, a, addr, -4);
@@ -6605,13 +6605,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a,
int rt2)
addr = op_addr_ri_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, rt2, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6644,13 +6644,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a,
int rt2)
addr = op_addr_ri_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rt2);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
op_addr_ri_post(s, a, addr, -4);
--
2.25.1
- [PATCH v2 00/24] target/arm: enforce alignment, Richard Henderson, 2020/12/08
- [PATCH v2 01/24] target/arm: Fix decode of align in VLDST_single, Richard Henderson, 2020/12/08
- [PATCH v2 02/24] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Richard Henderson, 2020/12/08
- [PATCH v2 03/24] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Richard Henderson, 2020/12/08
- [PATCH v2 05/24] target/arm: Fix SCTLR_B test for TCGv_i64 load/store, Richard Henderson, 2020/12/08
- [PATCH v2 06/24] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Richard Henderson, 2020/12/08
- [PATCH v2 04/24] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Richard Henderson, 2020/12/08
- [PATCH v2 09/24] target/arm: Enforce alignment for LDM/STM, Richard Henderson, 2020/12/08
- [PATCH v2 07/24] target/arm: Enforce word alignment for LDRD/STRD,
Richard Henderson <=
- [PATCH v2 08/24] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Richard Henderson, 2020/12/08
- [PATCH v2 11/24] target/arm: Enforce alignment for SRS, Richard Henderson, 2020/12/08
- [PATCH v2 10/24] target/arm: Enforce alignment for RFE, Richard Henderson, 2020/12/08
- [PATCH v2 12/24] target/arm: Enforce alignment for VLDM/VSTM, Richard Henderson, 2020/12/08
- [PATCH v2 14/24] target/arm: Enforce alignment for VLD1 (all lanes), Richard Henderson, 2020/12/08
- [PATCH v2 15/24] target/arm: Enforce alignment for VLDn/VSTn (multiple), Richard Henderson, 2020/12/08
- [PATCH v2 16/24] target/arm: Enforce alignment for VLDn/VSTn (single), Richard Henderson, 2020/12/08
- [PATCH v2 13/24] target/arm: Enforce alignment for VLDR/VSTR, Richard Henderson, 2020/12/08
- [PATCH v2 17/24] target/arm: Use finalize_memop for aa64 gpr load/store, Richard Henderson, 2020/12/08
- [PATCH v2 18/24] target/arm: Use finalize_memop for aa64 fpr load/store, Richard Henderson, 2020/12/08