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[PATCH v2 12/24] target/arm: Enforce alignment for VLDM/VSTM
From: |
Richard Henderson |
Subject: |
[PATCH v2 12/24] target/arm: Enforce alignment for VLDM/VSTM |
Date: |
Tue, 8 Dec 2020 12:01:06 -0600 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.c.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 96948f5a2d..98e4ae30eb 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -1065,12 +1065,12 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s,
arg_VLDM_VSTM_sp *a)
for (i = 0; i < n; i++) {
if (a->l) {
/* load */
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
vfp_store_reg32(tmp, a->vd + i);
} else {
/* store */
vfp_load_reg32(tmp, a->vd + i);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
}
tcg_gen_addi_i32(addr, addr, offset);
}
@@ -1148,12 +1148,12 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s,
arg_VLDM_VSTM_dp *a)
for (i = 0; i < n; i++) {
if (a->l) {
/* load */
- gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4);
vfp_store_reg64(tmp, a->vd + i);
} else {
/* store */
vfp_load_reg64(tmp, a->vd + i);
- gen_aa32_st64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4);
}
tcg_gen_addi_i32(addr, addr, offset);
}
--
2.25.1
- [PATCH v2 02/24] target/arm: Add ALIGN_MEM to TBFLAG_ANY, (continued)
- [PATCH v2 02/24] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Richard Henderson, 2020/12/08
- [PATCH v2 03/24] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Richard Henderson, 2020/12/08
- [PATCH v2 05/24] target/arm: Fix SCTLR_B test for TCGv_i64 load/store, Richard Henderson, 2020/12/08
- [PATCH v2 06/24] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Richard Henderson, 2020/12/08
- [PATCH v2 04/24] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Richard Henderson, 2020/12/08
- [PATCH v2 09/24] target/arm: Enforce alignment for LDM/STM, Richard Henderson, 2020/12/08
- [PATCH v2 07/24] target/arm: Enforce word alignment for LDRD/STRD, Richard Henderson, 2020/12/08
- [PATCH v2 08/24] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Richard Henderson, 2020/12/08
- [PATCH v2 11/24] target/arm: Enforce alignment for SRS, Richard Henderson, 2020/12/08
- [PATCH v2 10/24] target/arm: Enforce alignment for RFE, Richard Henderson, 2020/12/08
- [PATCH v2 12/24] target/arm: Enforce alignment for VLDM/VSTM,
Richard Henderson <=
- [PATCH v2 14/24] target/arm: Enforce alignment for VLD1 (all lanes), Richard Henderson, 2020/12/08
- [PATCH v2 15/24] target/arm: Enforce alignment for VLDn/VSTn (multiple), Richard Henderson, 2020/12/08
- [PATCH v2 16/24] target/arm: Enforce alignment for VLDn/VSTn (single), Richard Henderson, 2020/12/08
- [PATCH v2 13/24] target/arm: Enforce alignment for VLDR/VSTR, Richard Henderson, 2020/12/08
- [PATCH v2 17/24] target/arm: Use finalize_memop for aa64 gpr load/store, Richard Henderson, 2020/12/08
- [PATCH v2 18/24] target/arm: Use finalize_memop for aa64 fpr load/store, Richard Henderson, 2020/12/08
- [PATCH v2 19/24] target/arm: Enforce alignment for aa64 load-acq/store-rel, Richard Henderson, 2020/12/08
- [PATCH v2 21/24] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple), Richard Henderson, 2020/12/08
- [PATCH v2 20/24] target/arm: Use MemOp for size + endian in aa64 vector ld/st, Richard Henderson, 2020/12/08
- [PATCH v2 22/24] target/arm: Enforce alignment for aa64 vector LDn/STn (single), Richard Henderson, 2020/12/08