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Re: [PATCH v2 5/5] target/arm: add aarch32 ID register fields to cpu.h
From: |
Laurent Desnogues |
Subject: |
Re: [PATCH v2 5/5] target/arm: add aarch32 ID register fields to cpu.h |
Date: |
Tue, 15 Dec 2020 13:32:27 +0100 |
On Tue, Dec 15, 2020 at 12:52 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> Add entries present in ARM DDI 0487F.c (August 2020).
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Thanks,
Laurent
> ---
> target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index efa977eaca..fb81eed776 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1823,6 +1823,8 @@ FIELD(ID_ISAR6, DP, 4, 4)
> FIELD(ID_ISAR6, FHM, 8, 4)
> FIELD(ID_ISAR6, SB, 12, 4)
> FIELD(ID_ISAR6, SPECRES, 16, 4)
> +FIELD(ID_ISAR6, BF16, 20, 4)
> +FIELD(ID_ISAR6, I8MM, 24, 4)
>
> FIELD(ID_MMFR0, VMSA, 0, 4)
> FIELD(ID_MMFR0, PMSA, 4, 4)
> @@ -1833,6 +1835,24 @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
> FIELD(ID_MMFR0, FCSE, 24, 4)
> FIELD(ID_MMFR0, INNERSHR, 28, 4)
>
> +FIELD(ID_MMFR1, L1HVDVA, 0, 4)
> +FIELD(ID_MMFR1, L1UNIVA, 4, 4)
> +FIELD(ID_MMFR1, L1HVDSW, 8, 4)
> +FIELD(ID_MMFR1, L1UNISW, 12, 4)
> +FIELD(ID_MMFR1, L1HVD, 16, 4)
> +FIELD(ID_MMFR1, L1UNI, 20, 4)
> +FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
> +FIELD(ID_MMFR1, BPRED, 28, 4)
> +
> +FIELD(ID_MMFR2, L1HVDFG, 0, 4)
> +FIELD(ID_MMFR2, L1HVDBG, 4, 4)
> +FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
> +FIELD(ID_MMFR2, HVDTLB, 12, 4)
> +FIELD(ID_MMFR2, UNITLB, 16, 4)
> +FIELD(ID_MMFR2, MEMBARR, 20, 4)
> +FIELD(ID_MMFR2, WFISTALL, 24, 4)
> +FIELD(ID_MMFR2, HWACCFLG, 28, 4)
> +
> FIELD(ID_MMFR3, CMAINTVA, 0, 4)
> FIELD(ID_MMFR3, CMAINTSW, 4, 4)
> FIELD(ID_MMFR3, BPMAINT, 8, 4)
> @@ -1851,6 +1871,8 @@ FIELD(ID_MMFR4, LSM, 20, 4)
> FIELD(ID_MMFR4, CCIDX, 24, 4)
> FIELD(ID_MMFR4, EVT, 28, 4)
>
> +FIELD(ID_MMFR5, ETS, 0, 4)
> +
> FIELD(ID_PFR0, STATE0, 0, 4)
> FIELD(ID_PFR0, STATE1, 4, 4)
> FIELD(ID_PFR0, STATE2, 8, 4)
> @@ -1869,6 +1891,10 @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
> FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
> FIELD(ID_PFR1, GIC, 28, 4)
>
> +FIELD(ID_PFR2, CSV3, 0, 4)
> +FIELD(ID_PFR2, SSBS, 4, 4)
> +FIELD(ID_PFR2, RAS_FRAC, 8, 4)
> +
> FIELD(ID_AA64ISAR0, AES, 4, 4)
> FIELD(ID_AA64ISAR0, SHA1, 8, 4)
> FIELD(ID_AA64ISAR0, SHA2, 12, 4)
> @@ -1983,6 +2009,8 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
> FIELD(ID_DFR0, PERFMON, 24, 4)
> FIELD(ID_DFR0, TRACEFILT, 28, 4)
>
> +FIELD(ID_DFR1, MTPMU, 0, 4)
> +
> FIELD(DBGDIDR, SE_IMP, 12, 1)
> FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
> FIELD(DBGDIDR, VERSION, 16, 4)
> --
> 2.20.1
>
>
- [PATCH v2 2/5] target/arm: make ARMCPU.clidr 64-bit, (continued)
- [PATCH v2 2/5] target/arm: make ARMCPU.clidr 64-bit, Leif Lindholm, 2020/12/15
- [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Leif Lindholm, 2020/12/15
- Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Laurent Desnogues, 2020/12/15
- Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Leif Lindholm, 2020/12/15
- Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Laurent Desnogues, 2020/12/17
- Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Leif Lindholm, 2020/12/17
- Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Laurent Desnogues, 2020/12/17
- Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Leif Lindholm, 2020/12/17
[PATCH v2 5/5] target/arm: add aarch32 ID register fields to cpu.h, Leif Lindholm, 2020/12/15
- Re: [PATCH v2 5/5] target/arm: add aarch32 ID register fields to cpu.h,
Laurent Desnogues <=
Re: [PATCH v2 0/5] target/arm: various changes to cpu.h, Peter Maydell, 2020/12/15