[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 01/30] target/arm: Fix decode of align in VLDST_single
From: |
Richard Henderson |
Subject: |
[PATCH v3 01/30] target/arm: Fix decode of align in VLDST_single |
Date: |
Mon, 11 Jan 2021 09:00:44 -1000 |
The encoding of size = 2 and size = 3 had the incorrect decode
for align, overlapping the stride field. This error was hidden
by what should have been unnecessary masking in translate.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/neon-ls.decode | 4 ++--
target/arm/translate-neon.c.inc | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index c17f5019e3..0a2a0e15db 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -46,7 +46,7 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1
a:1 rm:4 \
VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
vd=%vd_dp size=0 stride=1
-VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \
vd=%vd_dp size=1 stride=%imm1_5_p1
-VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \
vd=%vd_dp size=2 stride=%imm1_6_p1
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index f6c68e30ab..0e5828744b 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -606,7 +606,7 @@ static bool trans_VLDST_single(DisasContext *s,
arg_VLDST_single *a)
switch (nregs) {
case 1:
if (((a->align & (1 << a->size)) != 0) ||
- (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
+ (a->size == 2 && (a->align == 1 || a->align == 2))) {
return false;
}
break;
@@ -621,7 +621,7 @@ static bool trans_VLDST_single(DisasContext *s,
arg_VLDST_single *a)
}
break;
case 4:
- if ((a->size == 2) && ((a->align & 3) == 3)) {
+ if (a->size == 2 && a->align == 3) {
return false;
}
break;
--
2.25.1
- [PATCH v3 00/30] target/arm: enforce alignment, Richard Henderson, 2021/01/11
- [PATCH v3 01/30] target/arm: Fix decode of align in VLDST_single,
Richard Henderson <=
- [PATCH v3 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Richard Henderson, 2021/01/11
- [PATCH v3 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B, Richard Henderson, 2021/01/11
- [PATCH v3 04/30] target/arm: Add wrapper macros for accessing tbflags, Richard Henderson, 2021/01/11
- [PATCH v3 05/30] target/arm: Introduce CPUARMTBFlags, Richard Henderson, 2021/01/11
- [PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base, Richard Henderson, 2021/01/11
- [PATCH v3 07/30] target/arm: Move TBFLAG_AM32 bits to the top, Richard Henderson, 2021/01/11
- [PATCH v3 08/30] target/arm: Move TBFLAG_ANY bits to the bottom, Richard Henderson, 2021/01/11
- [PATCH v3 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Richard Henderson, 2021/01/11
- [PATCH v3 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Richard Henderson, 2021/01/11
- [PATCH v3 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Richard Henderson, 2021/01/11