Re: [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension

[Richard Henderson]

On 1/12/21 12:45 AM, remi.denis.courmont@huawei.com wrote:
> From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> 
> This adds handling for the SCR_EL3.EEL2 bit.
> 
> Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

The patch title seems to have gone awry.

> @@ -2832,9 +2832,19 @@ static bool msr_banked_access_decode
>          }
>          if (s->current_el == 1) {
>              /* If we're in Secure EL1 (which implies that EL3 is AArch64)
> -             * then accesses to Mon registers trap to EL3
> +             * then accesses to Mon registers trap to Secure EL2, if it 
> exists,
> +             * otherwise EL3.
>               */
> -            TCGv_i32 tcg_el = tcg_const_i32(3);
> +            TCGv_i32 tcg_el;
> +
> +            if (dc_isar_feature(aa64_sel2, s)) {
> +                /* Target EL is EL<3 minus SCR_EL3.EEL2> */
> +                tcg_el = load_cpu_field(cp15.scr_el3);
> +                tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
> +                tcg_gen_addi_i32(tcg_el, tcg_el, 3);
> +            } else {
> +                tcg_el = tcg_const_i32(3);
> +            }

You can't test an aa64 feature without verifying that the cpu has aa64 support
(if the cpu is strictly aa32, the aa64 registers are undefined/uninitialized).  
So:

    if (arm_dc_feature(s, ARM_FEATURE_AARCH64) &&
        dc_isar_feature(aa64_sel2, s)) {
        ...

With those things changed,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~