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Re: [PATCH v4 0/8] target/arm: sve1 fixes
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v4 0/8] target/arm: sve1 fixes |
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Date: |
Thu, 11 Mar 2021 13:28:02 +0000 |
On Tue, 9 Mar 2021 at 15:53, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Three of these have been hanging around on a queue for ages;
> the rest are new. The WHILE and reduction bugs were found by
> RISU triggering an assertion on 384-bit (vq=3) vectors.
>
Applied to target-arm.next, thanks.
-- PMM
- [PATCH v4 0/8] target/arm: sve1 fixes, Richard Henderson, 2021/03/09
- [PATCH v4 1/8] target/arm: Fix sve_uzp_p vs odd vector lengths, Richard Henderson, 2021/03/09
- [PATCH v4 2/8] target/arm: Fix sve_zip_p vs odd vector lengths, Richard Henderson, 2021/03/09
- [PATCH v4 3/8] target/arm: Fix sve_punpk_p vs odd vector lengths, Richard Henderson, 2021/03/09
- [PATCH v4 4/8] target/arm: Update find_last_active for PREDDESC, Richard Henderson, 2021/03/09
- [PATCH v4 5/8] target/arm: Update BRKA, BRKB, BRKN for PREDDESC, Richard Henderson, 2021/03/09
- [PATCH v4 6/8] target/arm: Update CNTP for PREDDESC, Richard Henderson, 2021/03/09
- [PATCH v4 7/8] target/arm: Update WHILE for PREDDESC, Richard Henderson, 2021/03/09
- [PATCH v4 8/8] target/arm: Update sve reduction vs simd_desc, Richard Henderson, 2021/03/09
- Re: [PATCH v4 0/8] target/arm: sve1 fixes,
Peter Maydell <=