[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 14/16] target/arm: Implement ESB instruction
From: |
Peter Maydell |
Subject: |
Re: [PATCH 14/16] target/arm: Implement ESB instruction |
Date: |
Tue, 12 Apr 2022 10:56:44 +0100 |
On Mon, 11 Apr 2022 at 23:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/11/22 09:18, Peter Maydell wrote:
> >> + ESB ---- 0011 0010 0000 1111 ---- 0001 0000
> >> + ]
> >
> > Why don't we decode bits [11:8] here? I see it's the same
> > as YIELD/WFE/WFI, but I'm not sure why we're not decoding
> > those bits in those insns either...
>
> See page F4-7074 in H.a, where bits [11:8] of the imm12 field are described
> with 'xxxx'.
Hmm. That just means "decodes to the NOP/WFI/ESB/whatever
instruction-description whatever the value of those bits",
but when the specific instruction-description then marks
those bits as "(0)" or "(1)", that has the usual CONSTRAINED
UNPREDICTABLE meaning described in section F1.7.2, where
we get a free choice of UNDEF, NOP, ignore the bit, or
any-dest-regs-are-UNKNOWN. So we're within the spec to
not decode [11:8] but I think it would be more consistent
with how we try to handle those (0) and (1) bits generally
if we insist that [11:8] is all zeroes here.
For this series, I guess go along with the current way we
handle hint instructions, and maybe fix this as a separate
cleanup later.
-- PMM
- [PATCH 09/16] target/arm: Enable FEAT_Debugv8p4 for -cpu max, (continued)
[PATCH 15/16] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/08
[PATCH 10/16] target/arm: Add isar_feature_{aa64,any}_ras, Richard Henderson, 2022/04/08
[PATCH 13/16] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/04/08
[PATCH 16/16] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/04/08