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[PATCH v3 39/60] target/arm: Adjust definition of CONTEXTIDR_EL2
From: |
Richard Henderson |
Subject: |
[PATCH v3 39/60] target/arm: Adjust definition of CONTEXTIDR_EL2 |
Date: |
Sun, 17 Apr 2022 10:44:05 -0700 |
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Rely on EL3-no-EL2 squashing during registration.
---
target/arm/helper.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e762054b5d..3570212089 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7256,11 +7256,14 @@ static const ARMCPRegInfo jazelle_regs[] = {
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
};
+static const ARMCPRegInfo contextidr_el2 = {
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+ .access = PL2_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
static const ARMCPRegInfo vhe_reginfo[] = {
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
- .access = PL2_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -8222,6 +8225,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
}
+ if (cpu_isar_feature(aa64_vh, cpu) ||
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
+ }
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
define_arm_cp_regs(cpu, vhe_reginfo);
}
--
2.25.1
- [PATCH v3 30/60] target/arm: Name CPState type, (continued)
- [PATCH v3 30/60] target/arm: Name CPState type, Richard Henderson, 2022/04/17
- [PATCH v3 36/60] target/arm: Drop EL3 no EL2 fallbacks, Richard Henderson, 2022/04/17
- [PATCH v3 33/60] target/arm: Store cpregs key in the hash table directly, Richard Henderson, 2022/04/17
- [PATCH v3 34/60] target/arm: Cleanup add_cpreg_to_hashtable, Richard Henderson, 2022/04/17
- [PATCH v3 37/60] target/arm: Merge zcr reginfo, Richard Henderson, 2022/04/17
- [PATCH v3 38/60] target/arm: Add isar predicates for FEAT_Debugv8p2, Richard Henderson, 2022/04/17
- [PATCH v3 39/60] target/arm: Adjust definition of CONTEXTIDR_EL2,
Richard Henderson <=
- [PATCH v3 31/60] target/arm: Name CPSecureState type, Richard Henderson, 2022/04/17
- [PATCH v3 32/60] target/arm: Update sysreg fields when redirecting for E2H, Richard Henderson, 2022/04/17
- [PATCH v3 42/60] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 40/60] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Richard Henderson, 2022/04/17
- [PATCH v3 41/60] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/04/17