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[PATCH v3 48/60] target/arm: Add isar_feature_{aa64,any}_ras
From: |
Richard Henderson |
Subject: |
[PATCH v3 48/60] target/arm: Add isar_feature_{aa64,any}_ras |
Date: |
Sun, 17 Apr 2022 10:44:14 -0700 |
Add the aa64 predicate for detecting RAS support from id registers.
We already have the aa32 version from the M-profile work.
Add the 'any' predicate for testing both aa64 and aa32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 20bf70545e..d71edfc1c1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3885,6 +3885,11 @@ static inline bool isar_feature_aa64_aa32_el1(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
}
+static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
+}
+
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
@@ -4107,6 +4112,11 @@ static inline bool isar_feature_any_debugv8p2(const
ARMISARegisters *id)
return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
}
+static inline bool isar_feature_any_ras(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
+}
+
/*
* Forward to the above feature tests given an ARMCPU pointer.
*/
--
2.25.1
- [PATCH v3 40/60] target/arm: Move cortex impdef sysregs to cpu_tcg.c, (continued)
- [PATCH v3 40/60] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Richard Henderson, 2022/04/17
- [PATCH v3 41/60] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/04/17
- [PATCH v3 43/60] target/arm: Split out aa32_max_features, Richard Henderson, 2022/04/17
- [PATCH v3 45/60] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/04/17
- [PATCH v3 44/60] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/04/17
- [PATCH v3 46/60] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 47/60] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 48/60] target/arm: Add isar_feature_{aa64,any}_ras,
Richard Henderson <=
- [PATCH v3 49/60] target/arm: Add minimal RAS registers, Richard Henderson, 2022/04/17
- [PATCH v3 50/60] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/04/17
- [PATCH v3 52/60] target/arm: Implement ESB instruction, Richard Henderson, 2022/04/17
- [PATCH v3 53/60] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 51/60] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/04/17
- [PATCH v3 54/60] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 55/60] target/arm: Enable FEAT_CSV2 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 56/60] target/arm: Enable FEAT_CSV2_2 for -cpu max, Richard Henderson, 2022/04/17