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[PATCH v3 49/60] target/arm: Add minimal RAS registers
From: |
Richard Henderson |
Subject: |
[PATCH v3 49/60] target/arm: Add minimal RAS registers |
Date: |
Sun, 17 Apr 2022 10:44:15 -0700 |
Add only the system registers required to implement zero error
records. This means we need to save state for ERRSELR, but all
values are out of range, so none of the indexed error record
registers need be implemented.
Add the EL2 registers required for injecting virtual SError.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Leave ERRSELR_EL1 undefined.
v3: Rely on EL3-no-EL2 squashing during registration.
---
target/arm/cpu.h | 5 +++
target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 89 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d71edfc1c1..a6d1923a78 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -524,6 +524,11 @@ typedef struct CPUArchState {
uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
uint64_t gcr_el1;
uint64_t rgsr_el1;
+
+ /* Minimal RAS registers */
+ uint64_t disr_el1;
+ uint64_t vdisr_el2;
+ uint64_t vsesr_el2;
} cp15;
struct {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3570212089..655beba3d6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5990,6 +5990,87 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
};
+/*
+ * Check for traps to RAS registers, which are controlled
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
+ */
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ int el = arm_current_el(env);
+
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
+ return CP_ACCESS_TRAP_EL3;
+ }
+ return CP_ACCESS_OK;
+}
+
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ int el = arm_current_el(env);
+
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+ return env->cp15.vdisr_el2;
+ }
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+ return 0; /* RAZ/WI */
+ }
+ return env->cp15.disr_el1;
+}
+
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
+{
+ int el = arm_current_el(env);
+
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+ env->cp15.vdisr_el2 = val;
+ return;
+ }
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+ return; /* RAZ/WI */
+ }
+ env->cp15.disr_el1 = val;
+}
+
+/*
+ * Minimal RAS implementation with no Error Records.
+ * Which means that all of the Error Record registers:
+ * ERXADDR_EL1
+ * ERXCTLR_EL1
+ * ERXFR_EL1
+ * ERXMISC0_EL1
+ * ERXMISC1_EL1
+ * ERXMISC2_EL1
+ * ERXMISC3_EL1
+ * ERXPFGCDN_EL1 (RASv1p1)
+ * ERXPFGCTL_EL1 (RASv1p1)
+ * ERXPFGF_EL1 (RASv1p1)
+ * ERXSTATUS_EL1
+ * and
+ * ERRSELR_EL1
+ * may generate UNDEFINED, which is the effect we get by not
+ * listing them at all.
+ */
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
+ { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
+ .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
+ { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
+ .access = PL1_R, .accessfn = access_terr,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
+ { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
+};
+
/* Return the exception level to which exceptions should be taken
* via SVEAccessTrap. If an exception should be routed through
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
@@ -8224,6 +8305,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_ssbs, cpu)) {
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
}
+ if (cpu_isar_feature(any_ras, cpu)) {
+ define_arm_cp_regs(cpu, minimal_ras_reginfo);
+ }
if (cpu_isar_feature(aa64_vh, cpu) ||
cpu_isar_feature(aa64_debugv8p2, cpu)) {
--
2.25.1
- Re: [PATCH v3 40/60] target/arm: Move cortex impdef sysregs to cpu_tcg.c, (continued)
- [PATCH v3 41/60] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/04/17
- [PATCH v3 43/60] target/arm: Split out aa32_max_features, Richard Henderson, 2022/04/17
- [PATCH v3 45/60] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/04/17
- [PATCH v3 44/60] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/04/17
- [PATCH v3 46/60] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 47/60] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 48/60] target/arm: Add isar_feature_{aa64,any}_ras, Richard Henderson, 2022/04/17
- [PATCH v3 49/60] target/arm: Add minimal RAS registers,
Richard Henderson <=
- [PATCH v3 50/60] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/04/17
- [PATCH v3 52/60] target/arm: Implement ESB instruction, Richard Henderson, 2022/04/17
- [PATCH v3 53/60] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 51/60] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/04/17
- [PATCH v3 54/60] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 55/60] target/arm: Enable FEAT_CSV2 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 56/60] target/arm: Enable FEAT_CSV2_2 for -cpu max, Richard Henderson, 2022/04/17