[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 07/17] hw/registerfields: Add shared fields macros
From: |
Cédric Le Goater |
Subject: |
[PATCH v2 07/17] hw/registerfields: Add shared fields macros |
Date: |
Mon, 13 Jun 2022 15:25:29 +0200 |
From: Joe Komlodi <komlodi@google.com>
Occasionally a peripheral will have different operating modes, where the
MMIO layout changes, but some of the register fields have the same offsets
and behaviors.
To help support this, we add SHARED_FIELD_XX macros that create SHIFT,
LENGTH, and MASK macros for the fields that are shared across registers,
and accessors for these fields.
An example use may look as follows:
There is a peripheral with registers REG_MODE1 and REG_MODE2 at
different addreses, and both have a field FIELD1 initialized by
SHARED_FIELD().
Depending on what mode the peripheral is operating in, the user could
extract FIELD1 via
SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE1, FIELD1)
or
SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE2, FIELD1)
Signed-off-by: Joe Komlodi <komlodi@google.com>
Change-Id: Id3dc53e7d2f8741c95697cbae69a81bb699fa3cb
Message-Id: <20220331043248.2237838-2-komlodi@google.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/registerfields.h | 70 +++++++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 3a88e135d025..1330ca77de61 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -154,4 +154,74 @@
#define ARRAY_FIELD_DP64(regs, reg, field, val) \
(regs)[R_ ## reg] = FIELD_DP64((regs)[R_ ## reg], reg, field, val);
+
+/*
+ * These macros can be used for defining and extracting fields that have the
+ * same bit position across multiple registers.
+ */
+
+/* Define shared SHIFT, LENGTH, and MASK constants */
+#define SHARED_FIELD(name, shift, length) \
+ enum { name ## _ ## SHIFT = (shift)}; \
+ enum { name ## _ ## LENGTH = (length)}; \
+ enum { name ## _ ## MASK = MAKE_64BIT_MASK(shift, length)};
+
+/* Extract a shared field */
+#define SHARED_FIELD_EX8(storage, field) \
+ extract8((storage), field ## _SHIFT, field ## _LENGTH)
+
+#define SHARED_FIELD_EX16(storage, field) \
+ extract16((storage), field ## _SHIFT, field ## _LENGTH)
+
+#define SHARED_FIELD_EX32(storage, field) \
+ extract32((storage), field ## _SHIFT, field ## _LENGTH)
+
+#define SHARED_FIELD_EX64(storage, field) \
+ extract64((storage), field ## _SHIFT, field ## _LENGTH)
+
+/* Extract a shared field from a register array */
+#define SHARED_ARRAY_FIELD_EX32(regs, offset, field) \
+ SHARED_FIELD_EX32((regs)[(offset)], field)
+#define SHARED_ARRAY_FIELD_EX64(regs, offset, field) \
+ SHARED_FIELD_EX64((regs)[(offset)], field)
+
+/* Deposit a shared field */
+#define SHARED_FIELD_DP8(storage, field, val) ({ \
+ struct { \
+ unsigned int v:field ## _LENGTH; \
+ } _v = { .v = val }; \
+ uint8_t _d; \
+ _d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
+ _d; })
+
+#define SHARED_FIELD_DP16(storage, field, val) ({ \
+ struct { \
+ unsigned int v:field ## _LENGTH; \
+ } _v = { .v = val }; \
+ uint16_t _d; \
+ _d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
+ _d; })
+
+#define SHARED_FIELD_DP32(storage, field, val) ({ \
+ struct { \
+ unsigned int v:field ## _LENGTH; \
+ } _v = { .v = val }; \
+ uint32_t _d; \
+ _d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
+ _d; })
+
+#define SHARED_FIELD_DP64(storage, field, val) ({ \
+ struct { \
+ uint64_t v:field ## _LENGTH; \
+ } _v = { .v = val }; \
+ uint64_t _d; \
+ _d = deposit64((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
+ _d; })
+
+/* Deposit a shared field to a register array */
+#define SHARED_ARRAY_FIELD_DP32(regs, offset, field, val) \
+ (regs)[(offset)] = SHARED_FIELD_DP32((regs)[(offset)], field, val);
+#define SHARED_ARRAY_FIELD_DP64(regs, offset, field, val) \
+ (regs)[(offset)] = SHARED_FIELD_DP64((regs)[(offset)], field, val);
+
#endif
--
2.35.3
- [PATCH v2 00/17] aspeed: Extend ast2600 I2C model with new mode, Cédric Le Goater, 2022/06/13
- [PATCH v2 01/17] aspeed: Remove fake RTC device on ast2500-evb, Cédric Le Goater, 2022/06/13
- [PATCH v2 02/17] test/avocado/machine_aspeed.py: Move OpenBMC tests, Cédric Le Goater, 2022/06/13
- [PATCH v2 03/17] test/avocado/machine_aspeed.py: Add tests using buildroot images, Cédric Le Goater, 2022/06/13
- [PATCH v2 04/17] test/avocado/machine_aspeed.py: Add I2C tests to ast2500-evb, Cédric Le Goater, 2022/06/13
- [PATCH v2 05/17] test/avocado/machine_aspeed.py: Add I2C tests to ast2600-evb, Cédric Le Goater, 2022/06/13
- [PATCH v2 06/17] test/avocado/machine_aspeed.py: Add an I2C RTC test, Cédric Le Goater, 2022/06/13
- [PATCH v2 09/17] aspeed: i2c: Use reg array instead of individual vars, Cédric Le Goater, 2022/06/13
- [PATCH v2 11/17] aspeed: i2c: Add PKT_DONE IRQ to trace, Cédric Le Goater, 2022/06/13
- [PATCH v2 07/17] hw/registerfields: Add shared fields macros,
Cédric Le Goater <=
- [PATCH v2 10/17] aspeed: i2c: Add new mode support, Cédric Le Goater, 2022/06/13
- [PATCH v2 08/17] aspeed: i2c: Migrate to registerfields API, Cédric Le Goater, 2022/06/13
- [PATCH v2 12/17] aspeed: i2c: Move regs and helpers to header file, Cédric Le Goater, 2022/06/13
- [PATCH v2 13/17] aspeed/i2c: Add ast1030 controller models, Cédric Le Goater, 2022/06/13
- [PATCH v2 14/17] aspeed: Add I2C buses to AST1030 model, Cédric Le Goater, 2022/06/13
- [PATCH v2 15/17] hw/i2c/aspeed: rework raise interrupt trace event, Cédric Le Goater, 2022/06/13
- [PATCH v2 16/17] hw/i2c/aspeed: add DEV_ADDR in old register mode, Cédric Le Goater, 2022/06/13
- [PATCH v2 17/17] aspeed/i2c: Enable SLAVE_ADDR_RX_MATCH always, Cédric Le Goater, 2022/06/13