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[PATCH 13/14] target/arm/ptw: Report stage 2 fault level for stage 2 fau
From: |
Peter Maydell |
Subject: |
[PATCH 13/14] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw |
Date: |
Fri, 14 Jul 2023 16:46:47 +0100 |
When we report faults due to stage 2 faults during a stage 1
page table walk, the 'level' parameter should be the level
of the walk in stage 2 that faulted, not the level of the
walk in stage 1. Correct the reporting of these faults.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index ed46bb82a75..d1de934702d 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2046,9 +2046,13 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
do_translation_fault:
fi->type = ARMFault_Translation;
do_fault:
- fi->level = level;
- /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
- fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx);
+ if (fi->s1ptw) {
+ /* Retain the existing stage 2 fi->level */
+ assert(fi->stage2);
+ } else {
+ fi->level = level;
+ fi->stage2 = regime_is_stage2(mmu_idx);
+ }
fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx);
return true;
}
--
2.34.1
- Re: [PATCH 09/14] target/arm/ptw: Remove S1Translate::in_secure, (continued)
[PATCH 11/14] target/arm/ptw: Set attributes correctly for MMU disabled data accesses, Peter Maydell, 2023/07/14
[PATCH 10/14] target/arm/ptw: Drop S1Translate::out_secure, Peter Maydell, 2023/07/14
[PATCH 13/14] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw,
Peter Maydell <=
[PATCH 14/14] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types, Peter Maydell, 2023/07/14
[PATCH 12/14] target/arm/ptw: Check for block descriptors at invalid levels, Peter Maydell, 2023/07/14
[PATCH 03/14] target/arm/ptw: Set s1ns bit in fault info more consistently, Peter Maydell, 2023/07/14