[PATCH 5/8] hw/pci-host/designware: Keep host reference in DesignwarePCIEViewport

[Philippe Mathieu-Daudé]

The PCI root function is irrelevant for the ViewPort; only
a reference to the host bridge is required. Since we can
directly access the PCI bus, remove the pci_get_bus() call.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/pci-host/designware.h | 2 +-
 hw/pci-host/designware.c         | 7 +++----
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
index 9e2caa04e9..e1952ad324 100644
--- a/include/hw/pci-host/designware.h
+++ b/include/hw/pci-host/designware.h
@@ -32,7 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, 
DESIGNWARE_PCIE_HOST)
 OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT)
 
 typedef struct DesignwarePCIEViewport {
-    DesignwarePCIERoot *root;
+    DesignwarePCIEHost *host;
 
     MemoryRegion cfg;
     MemoryRegion mem;
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index fb46493a05..d12a36b628 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -211,12 +211,11 @@ static uint64_t designware_pcie_root_data_access(void 
*opaque, hwaddr addr,
                                                  uint64_t *val, unsigned len)
 {
     DesignwarePCIEViewport *viewport = opaque;
-    DesignwarePCIERoot *root = viewport->root;
+    PCIHostState *pci = PCI_HOST_BRIDGE(viewport->host);
 
     const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target);
     const uint8_t devfn  = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target);
-    PCIBus    *pcibus    = pci_get_bus(PCI_DEVICE(root));
-    PCIDevice *pcidev    = pci_find_device(pcibus, busnum, devfn);
+    PCIDevice *pcidev    = pci_find_device(pci->bus, busnum, devfn);
 
     if (pcidev) {
         addr &= pci_config_size(pcidev) - 1;
@@ -445,7 +444,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, 
Error **errp)
         g_free(name);
 
         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];
-        viewport->root    = root;
+        viewport->host    = host;
         viewport->inbound = false;
         viewport->base    = 0x0000000000000000ULL;
         viewport->target  = 0x0000000000000000ULL;
-- 
2.41.0