RE: [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ register fields

[Boddu, Sai Pavan]

>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ
>register fields
>
>Use de FIELD macro to describe the IRQ related register fields.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>

Reviewed-by: sai.pavan.boddu@amd.com


>---
> hw/net/cadence_gem.c | 51 +++++++++++++++++++++++++++++++++-------
>----
> 1 file changed, 39 insertions(+), 12 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>0acee1d544..6d084a3b31 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -155,13 +155,46 @@ REG32(RXSTATUS, 0x20) /* RX Status reg */
>     FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
>     FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
>     FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
>
> REG32(ISR, 0x24) /* Interrupt Status reg */
>+    FIELD(ISR, TX_LOCKUP, 31, 1)
>+    FIELD(ISR, RX_LOCKUP, 30, 1)
>+    FIELD(ISR, TSU_TIMER, 29, 1)
>+    FIELD(ISR, WOL, 28, 1)
>+    FIELD(ISR, RECV_LPI, 27, 1)
>+    FIELD(ISR, TSU_SEC_INCR, 26, 1)
>+    FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1)
>+    FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1)
>+    FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1)
>+    FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1)
>+    FIELD(ISR, PTP_SYNC_XMIT, 21, 1)
>+    FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1)
>+    FIELD(ISR, PTP_SYNC_RECV, 19, 1)
>+    FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1)
>+    FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1)
>+    FIELD(ISR, PCS_AN_COMPLETE, 16, 1)
>+    FIELD(ISR, EXT_IRQ, 15, 1)
>+    FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1)
>+    FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1)
>+    FIELD(ISR, PAUSE_FRAME_RECV, 12, 1)
>+    FIELD(ISR, RESP_NOT_OK, 11, 1)
>+    FIELD(ISR, RECV_OVERRUN, 10, 1)
>+    FIELD(ISR, LINK_CHANGE, 9, 1)
>+    FIELD(ISR, USXGMII_INT, 8, 1)
>+    FIELD(ISR, XMIT_COMPLETE, 7, 1)
>+    FIELD(ISR, AMBA_ERROR, 6, 1)
>+    FIELD(ISR, RETRY_EXCEEDED, 5, 1)
>+    FIELD(ISR, XMIT_UNDER_RUN, 4, 1)
>+    FIELD(ISR, TX_USED, 3, 1)
>+    FIELD(ISR, RX_USED, 2, 1)
>+    FIELD(ISR, RECV_COMPLETE, 1, 1)
>+    FIELD(ISR, MGNT_FRAME_SENT, 0, 1)
> REG32(IER, 0x28) /* Interrupt Enable reg */  REG32(IDR, 0x2c) /* Interrupt
>Disable reg */  REG32(IMR, 0x30) /* Interrupt Mask reg */
>+
> REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */  REG32(RXPAUSE, 0x38)
>/* RX Pause Time reg */  REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
>REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
>REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ @@ -306,16
>+339,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
>     FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*****************************************/
>
>
>-/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
>-#define GEM_INT_TXCMPL        0x00000080 /* Transmit Complete */
>-#define GEM_INT_AMBA_ERR      0x00000040
>-#define GEM_INT_TXUSED         0x00000008
>-#define GEM_INT_RXUSED         0x00000004
>-#define GEM_INT_RXCMPL        0x00000002
>
> #define GEM_PHYMNTNC_OP_R      0x20000000 /* read operation */
> #define GEM_PHYMNTNC_OP_W      0x10000000 /* write operation */
> #define GEM_PHYMNTNC_ADDR      0x0F800000 /* Address bits */
> #define GEM_PHYMNTNC_ADDR_SHFT 23
>@@ -1002,11 +1029,11 @@ static void gem_get_rx_desc(CadenceGEMState
>*s, int q)
>
>     /* Descriptor owned by software ? */
>     if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
>         DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n",
>desc_addr);
>         s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
>-        gem_set_isr(s, q, GEM_INT_RXUSED);
>+        gem_set_isr(s, q, R_ISR_RX_USED_MASK);
>         /* Handle interrupt consequences */
>         gem_update_int_status(s);
>     }
> }
>
>@@ -1102,11 +1129,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
>     /* Find which queue we are targeting */
>     q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
>
>     if (size > gem_get_max_buf_len(s, false)) {
>         qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
>-        gem_set_isr(s, q, GEM_INT_AMBA_ERR);
>+        gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
>         return -1;
>     }
>
>     while (bytes_to_copy) {
>         hwaddr desc_addr;
>@@ -1179,11 +1206,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
>
>     /* Count it */
>     gem_receive_updatestats(s, buf, size);
>
>     s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
>-    gem_set_isr(s, q, GEM_INT_RXCMPL);
>+    gem_set_isr(s, q, R_ISR_RECV_COMPLETE_MASK);
>
>     /* Handle interrupt consequences */
>     gem_update_int_status(s);
>
>     return size;
>@@ -1292,11 +1319,11 @@ static void gem_transmit(CadenceGEMState *s)
>                                                (p - s->tx_packet)) {
>                 qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \
>                          HWADDR_PRIx " too large: size 0x%x space 0x%zx\n",
>                          packet_desc_addr, tx_desc_get_length(desc),
>                          gem_get_max_buf_len(s, true) - (p - s->tx_packet));
>-                gem_set_isr(s, q, GEM_INT_AMBA_ERR);
>+                gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
>                 break;
>             }
>
>             /* Gather this fragment of the packet from "dma memory" to our
>              * contig buffer.
>@@ -1330,11 +1357,11 @@ static void gem_transmit(CadenceGEMState *s)
>                                          4 * gem_get_desc_len(s, false);
>                 }
>                 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
>
>                 s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
>-                gem_set_isr(s, q, GEM_INT_TXCMPL);
>+                gem_set_isr(s, q, R_ISR_XMIT_COMPLETE_MASK);
>
>                 /* Handle interrupt consequences */
>                 gem_update_int_status(s);
>
>                 /* Is checksum offload enabled? */ @@ -1380,11 +1407,11 @@ 
> static
>void gem_transmit(CadenceGEMState *s)
>
>         if (tx_desc_get_used(desc)) {
>             s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
>             /* IRQ TXUSED is defined only for queue 0 */
>             if (q == 0) {
>-                gem_set_isr(s, 0, GEM_INT_TXUSED);
>+                gem_set_isr(s, 0, R_ISR_TX_USED_MASK);
>             }
>             gem_update_int_status(s);
>         }
>     }
> }
>--
>2.39.2

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