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[RFC PATCH v2 04/22] target/arm: Implement ALLINT MSR (immediate)
From: |
Jinjie Ruan |
Subject: |
[RFC PATCH v2 04/22] target/arm: Implement ALLINT MSR (immediate) |
Date: |
Wed, 21 Feb 2024 13:08:05 +0000 |
Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra
to unwind.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
target/arm/tcg/a64.decode | 1 +
target/arm/tcg/helper-a64.c | 24 ++++++++++++++++++++++++
target/arm/tcg/helper-a64.h | 1 +
target/arm/tcg/translate-a64.c | 10 ++++++++++
4 files changed, 36 insertions(+)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 8a20dce3c8..3588080024 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -207,6 +207,7 @@ MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111
@msr_i
MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
+MSR_i_ALLINT 1101 0101 0000 0 001 0100 .... 000 11111 @msr_i
MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
# MRS, MSR (register), SYS, SYSL. These are all essentially the
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index ebaa7f00df..3686926ada 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -66,6 +66,30 @@ void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm)
update_spsel(env, imm);
}
+static void allint_check(CPUARMState *env, uint32_t op,
+ uint32_t imm, uintptr_t ra)
+{
+ /* ALLINT update to PSTATE. */
+ if (arm_current_el(env) == 0) {
+ raise_exception_ra(env, EXCP_UDEF,
+ syn_aa64_sysregtrap(0, extract32(op, 0, 3),
+ extract32(op, 3, 3), 4,
+ imm, 0x1f, 0),
+ exception_target_el(env), ra);
+ }
+}
+
+void HELPER(msr_i_allint)(CPUARMState *env, uint32_t imm)
+{
+ allint_check(env, 0x8, imm, GETPC());
+ if (imm == 1) {
+ env->allint |= PSTATE_ALLINT;
+ } else {
+ env->allint &= ~PSTATE_ALLINT;
+ }
+ arm_rebuild_hflags(env);
+}
+
static void daif_check(CPUARMState *env, uint32_t op,
uint32_t imm, uintptr_t ra)
{
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
index 575a5dab7d..3aec703d4a 100644
--- a/target/arm/tcg/helper-a64.h
+++ b/target/arm/tcg/helper-a64.h
@@ -22,6 +22,7 @@ DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_2(msr_i_spsel, void, env, i32)
DEF_HELPER_2(msr_i_daifset, void, env, i32)
DEF_HELPER_2(msr_i_daifclear, void, env, i32)
+DEF_HELPER_2(msr_i_allint, void, env, i32)
DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 340265beb0..f1800f7c71 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -2036,6 +2036,16 @@ static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i
*a)
return true;
}
+static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a)
+{
+ if (!dc_isar_feature(aa64_nmi, s) || s->current_el == 0) {
+ return false;
+ }
+ gen_helper_msr_i_allint(tcg_env, tcg_constant_i32(a->imm));
+ s->base.is_jmp = DISAS_TOO_MANY;
+ return true;
+}
+
static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a)
{
if (!dc_isar_feature(aa64_sme, s) || a->mask == 0) {
--
2.34.1
- [RFC PATCH v2 14/22] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), (continued)
- [RFC PATCH v2 14/22] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 15/22] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 21/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 12/22] hw/arm/virt: Wire NMI irq line from GIC to CPU, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 01/22] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 02/22] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 04/22] target/arm: Implement ALLINT MSR (immediate),
Jinjie Ruan <=
- [RFC PATCH v2 10/22] target/arm: Handle PSTATE.ALLINT on taking an exception, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 19/22] hw/intc/arm_gicv3: Add irq superpriority information, Jinjie Ruan, 2024/02/21