Re: [PATCH v3 08/16] aspeed/smc: support 64 bits dma dram address

[Cédric Le Goater]

Hello Jamin,


[ ... ]

> > See my aspeed-9.1 branch, I did some changes, mostly in the last patch.
> >
> > * aspeed_smc_dma_len()
> >
> >     - can use QEMU_ALIGN_UP(). simpler.
> >
> > * aspeed_smc_dma_rw():
> >
> >     - dram_addr ->  dma_dram_offset
> >     - There is no need to protect updates of the R_DMA_DRAM_ADDR_HIGH
> >       register with aspeed_smc_has_dma_dram_addr_high() since it is
> >       already protected with MMIO accesses. Skip the check and update
> >       always.
> >
> > * aspeed_smc_dma_dram_addr()
> >
> >     - same as above.
> >
> > You can merge the changes in the respective patches if you agree.
> >
> > Still on the TODO list :
> >
> >     - GIC review
> >     - aspeed/soc: fix incorrect dram size for AST2700
> >
> > Thanks,
> >
> > C.
> I merged this commit into my code base and thanks for your kindly support.
> https://github.com/legoater/qemu/commit/d1bc2c776422a9d0d6af2b4414fae83fde1832ba
>
> About GIC settings, you can refer to our kernel DTS setting for detail.
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi#L143-L164

Could you please resend a v4 including all the changes we discussed ?

Thanks,

C.